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DS35007B-page 36 2000 Microchip Technology Inc.
TABLE 7-2: PIC16CXXX INSTRUCTION SET
Mnemonic, Operands Description^ Cycles 14-Bit Opcode (^) Status MSb LSb^ Affected^ Notes BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF ANDWF CLRF CLRW COMF DECF DECFSZ INCF INCFSZ IORWF MOVF MOVWF NOP RLF RRF SUBWF SWAPF XORWF f, d f, d f
f, d f, d f, d f, d f, d f, d f, d f
f, d f, d f, d f, d f, d Add W and f AND W with f Clear f Clear W Complement f Decrement f Decrement f, Skip if 0 Increment f Increment f, Skip if 0 Inclusive OR W with f Move f Move W to f No Operation Rotate Left f through Carry Rotate Right f through Carry Subtract W from f Swap nibbles in f Exclusive OR W with f 1 1 1 1 1 1 1 (2) 1 1 (2) 1 1 1 1 1 1 1 1 1 C,DC,Z Z Z Z Z Z Z Z Z C C C,DC,Z Z 1, 1, 2 1, 1, 1,2, 1, 1,2, 1, 1, 1, 1, 1, 1, 1, BIT-ORIENTED FILE REGISTER OPERATIONS BCF BSF BTFSC BTFSS f, b f, b f, b f, b Bit Clear f Bit Set f Bit Test f, Skip if Clear Bit Test f, Skip if Set 1 1 1 (2) 1 (2) 1, 1, 3 3 LITERAL AND CONTROL OPERATIONS ADDLW ANDLW CALL CLRWDT GOTO IORLW MOVLW RETFIE RETLW RETURN SLEEP SUBLW XORLW k k k - k k k - k - - k k Add literal and W AND literal with W Call subroutine Clear Watchdog Timer Go to address Inclusive OR literal with W Move literal to W Return from interrupt Return with literal in W Return from Subroutine Go into standby mode Subtract W from literal Exclusive OR literal with W 1 1 2 1 2 1 1 2 2 2 1 1 1 C,DC,Z Z TO,PD Z TO,PD C,DC,Z Z Note 1: When an I/O register is modified as a function of itself ( e.g., ), the value used will be that value present 2: If this instruction is executed on the TMR0 register (and, where applicable, d = 1), the prescaler will be cleared if assigned to the Timer0 Module. 3: If Program Counter (PC) is modified or a conditional test is true, the instruction requires two cycles. The second cycle is executed as a. Note: Additional information on the mid-range instruction set is available in the PICmicro Mid-Range MCU Family Reference Manual (DS33023).
2000 Microchip Technology Inc. DS35007B-page 37 7.1 Instruction Descriptions ADDLW Add Literal and W Syntax: [ ] ADDLW k Operands: 0 k 255 Operation: (W) + k (W) Status Affected: C, DC, Z Description: The contents of the W register and the result is placed in the W register. ADDWF Add W and f Syntax: [ ] ADDWF f,d Operands: 0 f 127 d Operation: (W) + (f) (destination) Status Affected: C, DC, Z Description: Add the contents of the W register 1, the result is stored back in ANDLW AND Literal with W Syntax: [ ] ANDLW k Operands: 0 k 255 Operation: (W) .AND. (k) (W) Status Affected: Z Description: The contents of W register are 'k'. The result is placed in the W register. ANDWF AND W with f Syntax: [ ] ANDWF f,d Operands: 0 f 127 d Operation: (W) .AND. (f) (destination) Status Affected: Z Description: AND the W register with register 'f'. If 'd' is 0, the result is stored in the W register. If 'd' is 1, the result is stored back in register 'f'. BCF Bit Clear f Syntax: [ ] BCF f,b Operands: 0 f 127 0 b 7 Operation: 0 (f) Status Affected: None Description: Bit 'b' in register 'f' is cleared. BSF Bit Set f Syntax: [ ] BSF f,b Operands: 0 f 127 0 b 7 Operation: 1 (f) Status Affected: None Description: Bit 'b' in register 'f' is set. BTFSS Bit Test f, Skip if Set Syntax: [ ] BTFSS f,b Operands: 0 f 127 0 b < 7 Operation: skip if (f) = 1 Status Affected: None Description: If bit 'b' in register 'f' is '0', the next instruction is executed. If bit 'b' is '1', then the next instruc- tion is discarded and a is exe- cuted instead, making this a 2TCY instruction.
2000 Microchip Technology Inc. DS35007B-page 39 DECFSZ Decrement f, Skip if 0 Syntax: [ ] DECFSZ f,d Operands: 0 f 127 d [0,1] Operation: (f) - 1 (destination); skip if result = 0 Status Affected: None 1, the result is placed back in If the result is 1, the next instruc- tion is executed. If the result is 0, then a is executed instead, making it a 2TCY instruction. GOTO Unconditional Branch Syntax: [ ] GOTO k Operands: 0 k 2047 Operation: k PC<10:0> PCLATH<4:3> PC<12:11> Status Affected: None Description: is an unconditional branch. The eleven-bit immediate value is loaded into PC bits <10:0>. The upper bits of PC are loaded from PCLATH<4:3>. is a two- cycle instruction. INCF Increment f Syntax: [ ] INCF f,d Operands: 0 f 127 d [0,1] Operation: (f) + 1 (destination) Status Affected: Z 1, the result is placed back in INCFSZ Increment f, Skip if 0 Syntax: [ ] INCFSZ f,d Operands: 0 f 127 d [0,1] Operation: (f) + 1 (destination), skip if result = 0 Status Affected: None the result is placed back in If the result is 1, the next instruc- tion is executed. If the result is 0, a is executed instead, making it a 2TCY instruction. IORLW Inclusive OR Literal with W Syntax: [ ] IORLW k Operands: 0 k 255 Operation: (W) .OR. k (W) Status Affected: Z Description: The contents of the W register are The result is placed in the W register. IORWF Inclusive OR W with f Syntax: [ ] IORWF f,d Operands: 0 f 127 d [0,1] Operation: (W) .OR. (f) (destination) Status Affected: Z Description: Inclusive OR the W register with register 'f'. If 'd' is 0, the result is placed in the W register. If 'd' is 1, the result is placed back in register 'f'.
DS35007B-page 40 2000 Microchip Technology Inc. MOVF Move f Syntax: [ ] MOVF f,d Operands: 0 f 127 d [0,1] Operation: (f) (destination) Status Affected: Z Description: The contents of register f are moved to a destination dependant upon the status of d. If d = 0, des- tination is W register. If d = 1, the destination is file register f itself. d = 1 is useful to test a file register, since status flag Z is affected. MOVLW Move Literal to W Syntax: [ ] MOVLW k Operands: 0 k 255 Operation: k (W) Status Affected: None MOVWF Move W to f Syntax: [ ] MOVWF f Operands: 0 f 127 Operation: (W) (f) Status Affected: None Description: Move data from W register to register 'f'. NOP No Operation Syntax: [ ] NOP Operands: None Operation: No operation Status Affected: None Description: No operation. RETFIE Return from Interrupt Syntax: [ ] RETFIE Operands: None Operation: TOS PC, 1 GIE Status Affected: None RETLW Return with Literal in W Syntax: [ ] RETLW k Operands: 0 k 255 Operation: k (W); TOS PC Status Affected: None Description: The W register is loaded with the eight-bit literal 'k'. The program counter is loaded from the top of the stack (the return address). This is a two-cycle instruction. RETURN Return from Subroutine Syntax: [ ] RETURN Operands: None Operation: TOS PC Status Affected: None Description: Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program counter. This is a two-cycle instruction.
DS35007B-page 42 2000 Microchip Technology Inc. XORLW Exclusive OR Literal with W Syntax: [ ] XORLW k Operands: 0 k 255 Operation: (W) .XOR. k W) Status Affected: Z Description: The contents of the W register eral 'k'. The result is placed in the W register. XORWF Exclusive OR W with f Syntax: [ ] XORWF f,d Operands: 0 f 127 d [0,1] Operation: (W) .XOR. (f) destination) Status Affected: Z Description: Exclusive OR the contents of the W register with register 'f'. If 'd' is 0, the result is stored in the W register. If 'd' is 1, the result is stored back in register 'f'.
