1. Introduction
This laboratory activity involved the design and implementation of a full adder circuit. The full
adder was developed using both software and hardware methodologies. The software
implementation utilized Altera Quartus II for schematic entry and ModelSim for simulation. The
hardware implementation involved constructing the adder on a breadboard using 74xx-series
chips and programming it onto a DE2-115 FPGA board. The purpose of this lab was to gain a
deeper understanding of digital logic circuits, simulation techniques, and hardware
implementation.
2. Design, Testing and Documentation
2.1 Concept
The objective of the lab was to design and test a full adder circuit, a fundamental component in
digital arithmetic. The full adder takes three binary inputs (A, B, and Cin) and produces two
outputs: the sum (S) and the carry-out (Cout). This design ensures that the adder can be
cascaded to form multi-bit adders for larger arithmetic operations.
2.2 Implementation
2.2.1 Hardware Description
โ The full adder was built on a breadboard using XOR, AND, and OR gates.
โInputs were directly connected to the logic gates without using switches.
โOutputs were displayed using LED indicators.
Figure 1: Breadboard Implementation
2.2.2 Software Description
โ Schematic Entry: The full adder circuit was designed in Quartus II.
