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EECS
Midterm 10/5/ Professor Pister
Note: problem 1 and 2 are a little trickier than last semester! Read carefully!
- Given F = A’B’ + CD’ a. Write F’ in product of sums notation
b. Implement F using as few 2 input NOR gates as possible. Assume that only the true literals (A,B,C,D) are available, not their complements(A’, B’, C’, D’).
- Given G = (A’+ B’)(C+D’) a. Write G’ in sum of products notation.
b. Implement G using as few 2 input NAND gates as possible. Assume that only the true literals are available, not their complements.
- Answer the following questions for the FSM below: a. Briefly describe function of this sequence detector. When is the output 1?
b. Write a verilog module which would implement this FSM for input variable “In” and output variable “Out.” Use the same standard format as was presented in the Lab 3 lecture and used in Lab 3. (Define your states; use one always block for next state and output; use one always block for state transitions.
Mo 0
Ray 1
Star 0
Reset
- Design a 3 FlipFlop counter which transitions through states Q 2 Q 1 Q 0 = 000, 100, 110, 111, 011, 011 and then repeats.
a. Draw the state diagram and state transition table b. Draw the Karnaugh maps, clearly indicating the implicants that you use in your covers of the next-state functions. c. Implement the counter using D flip flops and whatever gates you like. d. Is your counter self starting? If yes, show the transitions of the unused states. If no, change it to make it self starting, and show the transitions of the unused states.
