Docsity
Log inSign up
Docsity
Prepare for your exams
Prepare for your exams

Study with the several resources on Docsity

Earn points to download
Earn points to download

Earn points by helping other students or get them with a premium plan

Guidelines and tips
Guidelines and tips
Sell on Docsity
Sell on Docsity
Log inSign up

Prepare for your exams

Study with the several resources on Docsity

Find documents

Prepare for your exams with the study notes shared by other students like you on Docsity

Search Store documents

The best documents sold by students who completed their studies

Search through all study resources
Docsity AINEW

Summarize your documents, ask them questions, convert them into quizzes and concept maps

Explore questions

Clear up your doubts by reading the answers to questions asked by your fellow students

Earn points to download

Earn points by helping other students or get them with a premium plan

Share documents
download point icon20 Points

For each uploaded document

Answer questions
download point icon5 Points

For each given answer (max 1 per day)

All the ways to get free points
Get points immediately

Choose a premium plan with all the points you need

Study Opportunities

Choose your next study program

Get in touch with the best universities in the world. Search through thousands of universities and official partners

Community

Ask the community

Ask the community for help and clear up your study doubts

University Rankings

Discover the best universities in your country according to Docsity users

Free resources

Our save-the-student-ebooks!

Download our free guides on studying techniques, anxiety management strategies, and thesis advice from Docsity tutors

From our blog

Exams and Study
Go to the blog

SPARC Registers, Windows - Computer Architecture - Lecture Slides, Slides of Computer Architecture and Organization

Himgiri Zee UniversityComputer Architecture and Organization

SPARC Registers, General purpose registers, Processor Status Register, Program Counters, Register Windows, Memory Organization, Addressing modes are the topics professor discussed in this class.

Typology: Slides

2011/2012

Uploaded on 11/03/2012

dharmaraaj
dharmaraaj 🇮🇳

4.4

(65)

153 documents

1 / 36

Toggle sidebar

This page cannot be seen from the preview

Don't miss anything!

bg1
1
SPARC Registers
•General purpose registers:32
immediately visible integer registers
and 32 floating point registers
•The Processor Status Register, PSR
contains the flags or condition codes
•Program Counters, PC and nPC hold
the current and next instruction
address
•Special purpose registers: WIM, TBR
and multiply step register Y.
Docsity.com
pf3
pf4
pf5
pf8
pf9
pfa
pfd
pfe
pff
pf12
pf13
pf14
pf15
pf16
pf17
pf18
pf19
pf1a
pf1b
pf1c
pf1d
pf1e
pf1f
pf20
pf21
pf22
pf23
pf24

Partial preview of the text

Download SPARC Registers, Windows - Computer Architecture - Lecture Slides and more Slides Computer Architecture and Organization in PDF only on Docsity!

1

SPARC Registers

  • General purpose registers:

immediately visible integer registers

and 32 floating point registers

  • The Processor Status Register, PSR

contains the flags or condition codes

  • Program Counters, PC and nPC hold

the current and next instruction

address

  • Special purpose registers: WIM, TBR

and multiply step register Y.

2

SPARC Registers

Processor State

Integer Registers

r

r

31 0

Floating Point Registers

r

r

31 0 nPC

(^31 )

(^31 )

(^31 )

(^31 )

(^31 )

(^31 )

PC

IR

Y

TBR

WIM

Multiply Step Register Trap base Register

Window Invalid mask

4

SPARC Register Window Mechanism

IN parameters Local registers OUT parameters

IN parameters Local registers OUT parameters

Current Window Pointer=N-

Current Window Pointer=N

save

restore

IN parameters

OUT parameters

Local registers

Current Window Pointer=N

r

r

Each window contains 32 registers, of which first 8 are global registers

r

r

Global Registers

5

Memory Organization

Memory Space 2 32 bytes

Word Size 32 bits

Memory Access 8, 16, 32 or 64 bits

Storage Format Big Endian

  • The memory specifications of the

SPARC processor are

7

SPARC Instruction formats

31 0 op displacement

29

All the SPARC instructionsare 32 bit wide. There are
three instruction formats as shown

1. Call

(^310) op a cond op2 disp

(^2928 2524 22 )

op (^) rd op2 disp

2a. Branches

2b. sethi

(^310) op op3 rs1 rs

29 25 24 19 opf

(^18141354)

op (^) rd op3 (^) rs1 0 asi op (^) rd op3 (^) rs1 (^1) simm

3a. Floating Point

3b. Data Movement

3c. ALU

rs

rd

8

Data Movement Instruction

Some commonly used data movement instructions are
Mnemonic opcode op3 Meaning
ldsb 11 001001 Load signed byte from address
ld 11 001000 Load signed word from address
ldd 11 000011 Load doubleword from address
stb 11 000101 Store byte to address
st 11 000100 Store word to address
or 10 000010 R[rd]←r[rs1] OR r[rs2] OR
immediate
sethi 00 Op2=100 Sets high order 22 bits of rd

10

SPARC Logic Instruction

Shifts/logic instructions of SPARC are

mnemonic op op3 meaning

And 10 0s0001 AND and set cc if S=

Andn 10 0s0101 NAND and set cc if S=

Or 10 0s0010 OR and set cc if S=

Orn 10 0s0110 NOR and set cc if S=

Xor 10 0s0011 XOR and set cc if S=

Xnor 10 0s0111 XNOR and set cc if S=

Sll 10 100101 Shift left logical rs1 by opnd2 bits into rd

Srl 10 100110 Shift right logical rs1 by opnd2 bits into rd

sra 10 100111 Shift right arithmetic rs1 by opnd2 bits into rd

11

SPARC Branch/Control Instruction

mnemonic format op Op
Op
Meaning
Bcc 2 00 010 Conditional branch
Ba 2 00 010 Unconditional branch
Call 1 01 Jump and link
Jmpl 3 10 11 1000 Jump and link
Save 3 10 11 1100 Provide new register
window
restore 3 10 11 1101 Restore old register
window

13

The Motorola MC

  • The first member of the 32 bit Motorola MC

family was introduced in 1979

  • It is based on a CISC architecture with a

number of complex instructions

  • The architecture is a variation of the general

register machine with separate registers

for address and data

  • The data path is 32 bit wide
  • There are 14 addressing modes

14

The Motorola MC

CPU Registers

  • PC There is a 32 bit PC that stores in its

least 24 bits the address of the next

instruction

  • IR The IR is a 16 bit register that holds the

first 16 bits of an instruction. For longer

instructions, the PC is incremented by 2

and the IR accesses next address

sequentially

  • D0-D7 These are the general data registers
  • A0-A7 Address Registers
  • CC The 16 bit status register containing flags

and condition codes

16

Memory Organization

Memory Space 2 24 bytes

Word Size 8, 16 or 32 bits

Storage Format Big Endian

  • The memory specifications of the

Mc68000 are

17

MC68000 addressing modes

Addressing mode Notation Operand Location

Data register direct Dn Dn

Address register direct An An

Address register indirect (An) Mem[An]

Autoincrement (An)+ Mem[An];An ← An+WS

Autodecrement -(An) An←An-WS;Mem[An]

Based Disp16(An) Mem[An+disp16]

Based indexed short Disp8(An,Xnlo) mem{[An+Xnlo+disp8]

Based indexed long Disp8(An,Xn) Mem[An+Xn+disp8]

Absolute short Addr16 Mem[addr16]

Absolute long Addr32 Mem[addr32]

Relative Disp16(PC) Mem[PC+disp16]

Relative indexed short Disp8(PC,xnlo) Mem[PC+Xnlo+disp8]

Relative indexed long Disp8(PC,Xn) Mem[PC+Xn+disp8]

Immediate #data nil

Low order 16 bits of any data or address register

Any of D0-D7 or A0-A

D0-D

A0-A

19

Data Movement Instruction

Some commonly used data movement instructions are
Mnemonic opcode operation operands Operand
size
MOVE.B 0001ddddddssssss dst←src EAs,EAd byte
MOVE.W 0011ddddddssssss dst←src EAs,EAd Word
MOVE.L 0010ddddddssssss dst←src EAs,EAd Longword
MOVEA.W 0011rrr001ssssss An ←src EAs,An Word
MOVEA.L 0010rrr001ssssss An ←src EAs,An Longword
LEA.L 0100aaa111ssssss An ←src EAs,An Address
EXG 1100xxx1mmmmm
yyy
Dx Dy Dx,Dy longword

Source effective address

Destination effective Any of the 8 address data registers

Any of the 8 data registers

Any of the 8 address registers

20

Arithmetic/Logic Instruction

Some commonly used arithmetic/logic instructions are

mnemonic opcode operation operands Operand size ADD 1101rrrmmmaaaaaa dst←dst+src EA,Dn b,w,l SUB 1001rrrmmmaaaaaa dst←dst-src EA,Dn b,w,l CMP 1011rrrmmmaaaaaa Dst-src EA,Dn b,w,l CMPI 00001100wwaaaaaa Dst-imm data #data,EA b,w,l MULS 1100rrr111aaaaaa Dn ←Dnsrc EA,Dn l ←ww DIVS 1000rrr111aaaaaa Dn ←Dn/src EA,Dn l ←l/w AND 1100rrrmmmaaaaaa dst←dst^src EA,Dn b,w,l OR 1000rrrmmmaaaaaa dst←dst~src EA,Dn b,w,l EOR 1011rrrmmmaaaaaa dst←dst⊗src EA,Dn b,w,l CLR 01000010wwaaaaaa dst← 0 EAs b,w,l NEG 01000100wwaaaaaa dst←0-dst Eas b,w,l TST 01001010wwaaaaaa dst-0 Eas b,w,l NOT 01000110wwaaaaaa dst←!dst EA b,w,l

Mode field

Destination register number

Address specifier