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UN IVERSIT Y OF CA LIFORNIA AT BERKELEY
BER KELEY • D AV IS • IR VIN E • LO S A N GELES • RIVERS ID E • S AN D IEGO • S AN FRANCIS CO SA NTA BA RBA RA • S AN TA CRU Z De p a r tm en t of Ele ctr i ca l En gin e e ri n g a n d Com p u t e r Sci en c es
CS 1 5 0 - Spr i n g 1 99 2 Pr o f. A. R. Ne wt o n
Quiz 2
Room 10 Evans, Tuesday 3/ (Open Katz, Calculators OK, 1hr 20min)
Include all final answers in locations indicated on these pages. Use reverse side of sheets for all working. If necessary, attach additional sheets by staple at the end. BE SURE TO WRITE YOUR NAME ON EVERY SHEET.
(1) (a) The binary string “ 10110101 ” is the 8-bit two’s complement representation of a fixed point number. What is its decimal value?
1(a) (5pts) 10110101 = _______ 10
(b) Design a circuit to compute the two’s complement of a 3-bit binary number. The inputs are b 0 , b 1 and b 2 , where b 2 is the most significant digit and the outputs are c 0 , c 1 and c 2 where c 2 is the most significant digit.
(i) Show a truth table for the circuit. (ii) Draw Karnaugh maps for each output and use them to simplify the functions. (iii) Draw a schematic diagram using the minimum number of NAND gates and inverters only.
1(b) (15pts)
(i) Truth table:
1(b) (ii) Karnaugh Maps:
00 01 11 10 0
1
0 (^1375)
(^264)
00 01 11 10 0 1
0 (^1375)
2 6 4
00 01 11 10 0 1
0 1 3 7 5
2 6 4
(iii) Schematic diagram:
2(c) (i) (2pts) Karnaugh Maps:
(ii) (6pts) Flip-flop Input Equations & clock generation:
_____________________________________________
_____________________________________________
CLK = _____________
(iii) (4pts) Output Equations:
N = ________________ E = _________________
S = ________________ W = ________________
(iv) (7pts) Schematic Diagram:
(3) Consider the state table for a Mealy machine shown below:
next state output Z
x=0 x=1 x=0 x=
S 0 S 1 S 2 0 0
S 1 S 3 S 2 0 0
S 2 S 1 S 4 0 0
S 3 S 5 S 2 0 0
S 4 S 1 S 6 0 0
S 5 S 5 S 2 1 0
S 6 S 1 S 6 0 1
(a) Draw a state transition graph for the machine showing all input/output transitions and symbolic states. (b) Use the guidelines presented in class for state assignment to select an optimal state assignment (for minimum logic). Show all constraints , your final state assignment , and indicate which constraints are not satisfied by the assignment. (c) If a ROM where used to implement the next-state and output logic for a D-flip-flop-based implementation of your machine, how big would it have to be?
3(a) (4 pts) State Transition Graph:
