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RARD Queueing - Design and Analysis of Switching Systems - Exam, Exams of Design and Analysis of Algorithms

Main points of this exam paper are: Independently Each Cycle, Queueing Model, Probability, Arriving Cell, Steady-State Probabilities, Expressions, Cell Loss Probability, Average Queue Length, Data Structure, Address Prefixes

Typology: Exams

2012/2013

Uploaded on 03/23/2013

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Exam 1, Part A
February 26, 1999
This part of the exam is closed book. Be neat and show your work in the space provided.
1. (15 points) Consider the RARD queueing model in which cells arrive independently each cycle with
probability
๎˜•
, leave with probability
๎˜–
and an arriving cell is discarded if the queue is full and no cell
leaves in that time step. Give equations for the steady-state probabilities
๎˜™
(
0
)
;:::;๎˜™
(
B
)
in terms of
๎˜•
,
๎˜–
and
B
.
Give expressions for the average queue length and for the cell loss probability.
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Exam 1, Part A

February 26, 1999

This part of the exam is closed book. Be neat and show your work in the space provided.

  1. (15 points) Consider the RARD queueing model in which cells arrive independently each cycle with probability , leave with probability  and an arriving cell is discarded if the queue is full and no cell leaves in that time step. Give equations for the steady-state probabilities  ( 0 ); : : : ;  (B ) in terms of ,  and B.

Give expressions for the average queue length and for the cell loss probability.

  1. (15 points) The figure below shows a data structure for IP address lookup using a trie. In the figure, the nodes containing numbers correspond to valid address prefixes and the numbers are the output ports that should be used by packets for which a given prefix is the best match.

If a packet with destination address a3b2ff75 is received, what output port should it be forwarded on (the address is given in hexadecimal notation)?

What about packets with addresses 32fecd91 and 725cd401?

Show how the data structure must be changed to include a new prefix 101101* with next hop 22. Show how it must be changed to include a new prefix 01001* with next hop 17.

How many bits per second are carried on the links into and out of the backbone switch if the routing tables only have an entry for 80% of the packets received?

  1. (15 points) Consider an ATM switch with a bus interconnecting the input and output port processors. Suppose that each cell time, input 2 receives a cell that is to be forwarded to output 0 with probability p 1 and that input 7 receives a cell for output 0 with probability p 2. Assume that all cell arrivals are independent. If we start observing output 0 at time t, what is the probability that the next cell for output 0 from input 2 arrives at time t + i?

What is the probability that the next cell to be received from input 7 arrives at time t + i?

What is the probability that the next cell from either input 2 or input 7 arrives at time t + i?

What is the probability that the next cell from input 2 arrives at the same time or before the next cell from input 7?

  1. (15 points) Suppose there are 20 different virtual circuits sharing a 150 Mb/s link and the queue controller at the sending end of the link implements Early Packet Discard. 6 of the 20 data sources using the virtual circuits are sending packets with 50 cells each at a rate of 50 Mb/s and the remaining 14 are sending packets with 20 cells each at a rate of 10 Mb/s. Using a worst-case analysis, how much memory is required at the output queue to ensure 100% goodput during the overload period? What should the threshold value be?

Suppose that all 20 sources send data at 25 Mb/s, with a packet length of 50 cells. Using the even offset analysis method, how much memory is required for 100% goodput? What should the threshold value be?

  1. (15 points) Consider an ATM switching system with 32 ports and a crossbar interconnection network, that supports independent label multicast. If the input and output links each support 8192 virtual circuits and if at most 25% of the outgoing VCIs are used by multicast virtual circuits, how many routing table entries are needed in each input port processor? How many bytes per entry, assuming both unicast and multicast virtual circuits. You may assume that the system only switches on VCIs (VPIs are ignored on input and set to 0 on output).

How many entries are needed in each OPP routing table, assuming that the OPPs use direct lookup tables? How many bytes per entry?

How many entries are needed in each OPP routing table, assuming that the OPPs use CAMs? How many bytes per entry? If the cost per bit of the CAM is 5 times the cost per bit of standard memory, what is the relative cost of the two alternatives?

  1. (15 points) Consider a switch that handles fixed length cells of 500 bits and has 20 links that run at 500 Mb/s. The switch has an internal bus that is 50 bits wide and carries each cell as a sequence of 11 words. Assume that the bus clock frequency is 55 MHz. If all links are loaded equally, what is the maximum permissible loading level on the input links that does not overload the bus.

Assume that data is arriving on inputs 0, 3, 8, 11 and 15 at 500 Mb/s and that data is arriving on inputs 1, 4, 9, 13 and 19 at 250 Mb/s. If bus arbitration is done using a simple static daisy chain arbitration mechanism in which input 0 always gets the first opportunity to use the bus, how much of the bus bandwidth do each of the inputs get?

Suppose that the bus arbitration is done using daisy chain arbitration in which the starting point is rotated by one position after each bus cycle (so if input 0 gets the first chance to use the bus during one bus cycle, then input 1 gets the first chance in the next bus cycle). How much of the bus bandwidth do each of the inputs get in this case?

Suppose the bus arbitration is done using daisy chain arbitration in which the starting point is rotated just past the winner of the previous bus cycle (that is, if input i uses the bus in one bus cycle, then input i + 1 is first in the daisy chain in the next bus cycle. How much of the bus bandwidth do each of the inputs get in this case?

Give an expression for the virtual cell discard probability at the output queue of the first switch.

Give an expression for the congestion probability at the output queue of the first switch.

Let x 1 denote the cell discard probability obtained using the IBA model. Let x 2 denote the virtual cell discard probability. Let x 3 denote the congestion probability and let x 4 be the value for the cell loss probability obtained using a fluid simulation of the output queue. Without doing any calculations, list the xi in order from the smallest to the largest.

Suppose that active sources send data at 150 Mb/s instead of 20 Mb/s and that the buffer can hold up to 200,000 cells instead of 2,000. List the xi in order from smallest to largest under this assumption.

  1. (60 points) Consider a crossbar-based switch with per-input queues in the IPPs. The figure below shows the IPPs and the number of cells in their per output queues.

       

       

       

       

       

       

       

       



      

      



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Suppose that during an arbitration cycle, each IPP sends the crossbar controller a bit vector specifying which of its queues are non-empty and that the crossbar controller uses an iterative matching algorithm to select which IPPs get to send in each cycle, based on the empty/non-empty status of their queues. Assume that whenever an output is requested by more than one input, the controller grants permission to send, to the input with the smallest index (that is, if input i and input j , both select output k and i < j , then the controller selects input i). If an input gets grants for more than one output, the controller accepts the grant for the output with the smallest index. For the example situation shown above, show which inputs are selected to send cells by the crossbar controller assuming that the crossbar controller implements three iterations of the iterative matching algorithm. Show which outputs, each selected input is matched to.

Suppose that the IPPs send the crossbar controller the number of cells in each of their per-output queues, rather than just a bit vector and that the crossbar controller uses this information in the iterative matching algorithm. In particular, assume that when several inputs request a given output, the controller selects the input with the longest queue (assume ties are broken in favor of the input with the smallest index). If an input is selected by multiple outputs, the controller matches it with the output for which it has the most waiting cells. For the example above, show which inputs are selected by the iterative matching algorithm in this case and which outputs they are matched to. Assume that in this case, only two iterations are performed.

The iterative matching algorithm does not always match inputs to outputs in the best possible way. Consequently, some of the switch bandwidth can be wasted. Show that there are worst-case traffic patterns in which the first version of the iterative matching algorithm causes half of the crossbar bandwidth to be wasted, even if we allow an unlimited number of iterations. Can the performance be any worse than this? Why or why not? How does the second version of the iterative matching algorithm perform for the traffic pattern that causes the first version to perform badly?