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Processor State Using RTL - Computer Architecture - Lecture Slides, Slides of Computer Architecture and Organization

Himgiri Zee UniversityComputer Architecture and Organization

Processor State, RTL, Dynamic Properties, FALCON A, Effective Address Calculations, Relative Address, Range of Memory Addresses are the topics professor discussed in class.

Typology: Slides

2011/2012

Uploaded on 11/03/2012

dharmaraaj
dharmaraaj 🇮🇳

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1
Fields in the FALCON-A Instruction
op〈4..0〉 := IR〈15..11〉:operation code field
ra〈2..0〉 := IR〈10..8〉: target register field
rb〈2..0〉 := IR〈7..5〉: operand or address index
rc〈2..0〉 := IR〈4..2〉: second operand
c1〈4..0〉 := IR〈4..0〉: short displacement field
c2〈7..0〉 := IR〈7..0〉: long displacement or
immediate field
RTL naming operator
Docsity.com
pf3
pf4
pf5
pf8
pf9
pfa
pfd
pfe
pff
pf12
pf13
pf14
pf15
pf16
pf17
pf18
pf19
pf1a
pf1b
pf1c
pf1d
pf1e
pf1f

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Download Processor State Using RTL - Computer Architecture - Lecture Slides and more Slides Computer Architecture and Organization in PDF only on Docsity!

1

Fields in the FALCON-A Instruction

op〈4..0〉 := IR〈15..11〉:operation code field

ra〈2..0〉 := IR〈10..8〉: target register field

rb〈2..0〉 := IR〈7..5〉: operand or address index

rc〈2..0〉 := IR〈4..2〉: second operand

c1〈4..0〉 := IR〈4..0〉: short displacement field

c2〈7..0〉 := IR〈7..0〉: long displacement or

immediate field

RTL naming operator

2

Describing the Processor

State Using RTL

Processor State

PC<15..0>: program counter

(memory address of next

instruction)

IR〈15..0〉: instruction register

Run: one bit run/halt indicator

Strt: start signal

R[0..7]〈15..0〉: general purpose

registers

4

Effective Address Calculations in RTL

(Performed At Runtime)

  • Displacement Address

disp〈15..0〉 := ( R[rb] + ( 11 α C1<4> ) © C1<4..0> );

  • Relative Address

rel〈15..0〉 := PC + ( 8 α C2<7> ) © C2<7..0>;

Sign Extension

Sign Extension

5

  • Using Direct Addressing (Displacement with

rb=0)

 If c1〈 4 〉=0 (positive displacement) absolute addresses range: 00000b to 01111b (0 to +15)  If c1〈 4 〉=1 (negative displacement) absolute addresses range: 11111b to 10000b (-1 to -16)

  • Using Relative Addressing

 The largest positive value of C2〈7..0〉 is 2 7 -1 and its most negative value is -2 7 , so addresses up to 127 locations forward and 128 locations backwards from the current PC value can be specified

Range of Memory Addresses

7

Flow diagram

Instruction Fetch

Instruction Decode

Op-code = 0

Op-code = 30 Op-code = 1

Op-code = 31 …

appropriate processing goes in this place

8

Instruction Execution

(Jump Instructions)

ie := (

... ... (op<4..0> = 20) : ( cond : PC ← R[ra] + c2(sign extended) ), unconditional branch (jump) (op<4..0> = 16) : cond : ( PC ← PC + C2(sign extended) ), conditional jump (jpl) ... ...

10

Instruction Execution

(Shift Instructions)

ie := (

... ...

(op<4..0>=12) : R[ra]〈15..0 〉 ← R[rb]<( 15 – N )..0> © ( N α 0 ); (op<4..0>=13) : R[ra]〈15..0 〉 ← ( N α 0 ) © R[rb]<15..N>; (op<4..0>=15) : R[ra]〈15..0 〉 ← N α ( R[rb]<15> ) © ( R[rb]<15..N> );

... ...

Notation: α means replication © means concatenation

Shift

Shift Right

Left

Arithmetic Shift Right

11

Instruction Execution

(Data Transfer Instructions)

ie := (

... ...

(op<4..0>=29) : R[ra] ← M[R[rb] + (11 α C1<4>) © C1<4..0>];

(op<4..0>=28) : M[R[rb] + (11 α C1<4>) © C1<4..0>] ← R[ra];

(op<4..0>=6) : R[ra] ← R[rb];

(op<4..0>=7) : R[ra] ← (8 α C2<7>) © C2<7..0>;

(op<4..0>=24) : R[ra] ← IO[c2];

(op<4..0>=25) : IO[c2] ← R[ra];

... ...

load store mov movi

in

out

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