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The cs152 computer architecture and engineering midterm i exam from university of california, berkeley, college of engineering, eecs, spring 1999. The exam covers topics such as performance analysis, full adder design, unsigned division algorithm, and adding new instructions to a single-cycle datapath. Students are required to analyze benchmarks, implement circuits, and write pseudo-code.
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University of California, Berkeley College of Engineering Computer Science Division EECS
Spring 1999 John Kubiatowicz
March 3, 1999 CS152 Computer Architecture and Engineering
Your Name:
SID Number:
Discussion Section:
Problem Possible Score
1 15
2 15
3 20
4 20
5 30
Total
Problem 1c: What is the CPI and MIPS rating of the new processor?
Problem 1d: What is the original cost per (working) processor?
Problem 1e: What is the new cost per (working) processor?
Problem 1f: What is the improvement (if any) in price per performance?
Problem 2: Delay For a Full Adder
A key component of an ALU is a full adder. A symbol for a full adder is:
Problem 2a: Implement a full adder using as few 2-input AND, OR, and XOR gates as possible. Keep in mind that the Carry In signal may arrive much later than the A or B inputs. Thus, optimize your design (if possible) to have as few gates between Carry In and the two outputs as possible:
Full Adder
A B
S
Cout C (^) in
Problem 3: Division Here is pseudo-code for an unsigned division algorithm. It is essentially the last divider (#3) that we developed in class. Assume that quotient and remainder are 32-bit global values, and the inputs divisor and dividend are also 32 bits.
divide(dividend, divisor) { int count;
/* Missing initialization instructions. */
ROL64(remainder,quotient,0); while (count > 0) { count--; if (remainder ≥ divisor) { remainder = remainder – divisor; temp = 1; } else { temp = 0; } ROL64(remainder,quotient,temp); } /* Something missing here */ }
The ROL64(hi,lo,inbit) pseudo-instruction treats hi and lo together as a 64-bit register. Assume that inbit contains only 0 or 1. ROL64 shifts the combined register left by one position, filling in the single bit from inbit into the lowest bit of lo.
Problem 3a: Implement ROL64 as 5 MIPS instructions. Assume that $t0, $t1, and $t2 are the arguments. Hint: what happens if you use signed slt on unsigned numbers?
Problem 3b: This divide algorithm is incomplete. It is missing some initialization and some final code. What is missing?
Problem 3c: Assume that you have a MIPS processor that is missing the divide instruction. Implement the above divide operation as a procedure. Assume dividend and divisor are in $a0 and $a1 respectively, and that remainder and quotient are returned in registers $v0 and $v respectively. You can use ROL64 as a pseudo-instruction that takes 3 registers. Don’t use any other pseudo-instructions, however. Make sure to adher to MIPS register conventions, and optimize the loop as much as possible.
Problem 3d: What is the “CPI” of your divide procedure (i.e. what is the total number of cycles to perform a divide)? Assume that each MIPS instruction takes 1 cycle.
Problem 4: New instructions for a single-cycle data path
The Single-Cycle datapath developed in class is shown below (similar to the one in the book):
It supports the following instructions. (Note that, as in the virtual machine, the branch is not delayed.) op | rs | rt | rd | shamt | funct = MEM[PC] op | rs | rt | Imm16 = MEM[PC]
INST Register Transfers
ADDU R[rd] ← R[rs] + R[rt]; PC ← PC + 4 SUBU R[rd] ← R[rs] - R[rt]; PC ← PC + 4 ORI R[rt] ← R[rs] + zero_ext(Imm16); PC ← PC + 4 LW R[rt] ← MEM[ R[rs] + sign_ext(Imm16)]; PC ← PC + 4 SW MEM[R[rs] + sign_ext(Imm16)] ← R[rs]; PC ← PC + 4 BEQ if ( R[rs] == R[rt] ) then PC ← PC + sign_ext(Imm16)∪ 00 else PC ← PC + 4
Consider adding the following instructions: ADDIU, XOR, JAL , and BGEZAL (branch on greater than or equal to zero and link). This last instruction branches if the value of register rs ≥ 0; further, it saves the address of the next instruction in $ra (like JAL). Remember that the JAL format has a 6-bit opcode + 26 bits used as an offset...
imm
32
ALUctr
Clk
busW
RegWr
32
32
busA
32
busB
5 5 5 Rw Ra Rb 32 32-bit Registers
Rs
Rt
Rt
Rd
RegDst
Extender
Mux
imm16 16 32
ExtOp ALUSrc
Mux
MemtoReg
Clk
Data In
(^32) WrEn Adr Data Memory
MemWr
ALU
Equal
Instruction<31:0>
0
1
0
1
1 0
<21:25><16:20><11:15><0:15>
Rs Rt Rd Imm
=
Adder
Adder
PC
Clk
00 Mux
4
nPC_sel
PC Ext
Adr
Inst Memory
3
Problem 4a : Describe/sketch the modifications needed to the datapath for each instruction. Try to add as little hardware as possible. Make sure that you are very clear about your changes. Also assume that the original datapath had only enough functionality to implement the original 5 instructions:
Problem 4b : Specify control for each of the new instructions. Make sure to include values (possibly “x”) for all of the control points.
[ Problem 5 continued ] Single-bit Booth encoding results from noticing that a sequence of ones can be represented by two non-zero values at the endpoints:
The encoding uses three symbols, namely: 1 , 0 ,DQG. (The 1 stands for “-1”). A
more complicated example of Booth encoding, used on a two’s-compliment number is the following:
To perform Booth encoding, we build a circuit that is able to recognize the beginning, middle, and end of a string of ones. When encoding a string of bits, we start at the far right. For each new bit, we base our decision of how to encode it on both the current bit and the previous bit (to the right).
Problem 5c: Write a table describing the this encoding. It should have 2 input bits (current and previous) and should output a 2 bit value which is the two’s compliment value of the
encoded digit (representing 1 , 0 ,or 1 ):
Problem 5d: Modify your datapath to do 32x32 bit signed multiplication by Booth-encoding the multiplier (the operand which is shifted during multiplication). Draw the Booth-encoder as a black-box in your design that takes two bits as input and produces a 2-bit, two’s complement encoding on the output. Assume that you have a 32-bit ALU that can either add or subtract. (Hint: Be careful about the sign-bit of the result during shifts. Also, be careful about the initial value of the “previous bit”.) Explain how how your algorithm is different from the previous multiplier.
Problem 5g [Extra Credit]: Draw a datapath that does signed multiplication, two bits at a time and include the multiplication algorithm. Draw the two-bit Booth encoder as a black box which implements output from the table in problem 5f. Make sure that you describe how the 5
possible output symbols (i.e. 2 , 1 , 0 , 1 ,and 2 ) are encoded (hint: two’s complement is not
the best solution here). As before, assume that you have a 32-bit ALU that can add and subtract:
