Network Connecting - Computer Engineering - Solved Exam, Exams of Computer Science

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ECE 2030

Section F

Midterm II Solutions

Fall 2004

Building Blocks

1. Implement a full adder using only two, 4-to-1 multiplexors.

A B Ci S Co 0 0 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 1 0 1 1 0 0 1 0 1 0 1 0 1 1 1 0 0 1 1 1 1 1 1

3. The following figure shows a 8 x 4 bit ROM where an X represents the fact that a fuse was blown. Fill in the truth table below.

Number Systems

4. Convert the following numbers from one notation to the other. a. Between radices

(1100.0011) 2 = 14.14 (^8) (178) 16 = 1(16) 2 + 7(16) + 8(1) = 376 10 (46.5625) 10 = 101110.1001 (^2)

b. Convert 46.25 to IEEE 754 single precision format and provide the hexadecimal value of the encoding.

First convert 46.25 to binary = 101110. Since the number is +ve sign bit is 0. Rewriting the number 1.0111001 x 2^5. Expanding the fraction to 23 bits 01110010000000000000000. The exponent is 5. Biasing 5 + 127 = 132. In binary this is 10000100. Putting this all together 01000010001110010000000000000000 0x

5. Fill in the following table for the ranges of an n -digit binary number using the stated representation. Type Smallest number Largest number Unsigned integer 0 2 n^ - 1

Two’s Complement -2 n-1^2 n-1^ - 1

Sign Magnitude -2n-1^ - 1 2 n-1^ - 1

8. Draw the figure for a 3-bit Adder/Subtractor using the following building blocks: FA (full adder), multiplexors, and basic gates. Include circuitry for producing two additional signals: OVRFLW which indicates that overflow has occurred and PST which indicates that the result of the operation is positive. Label all inputs, outputs, and connections clearly. All connections should be shown.

Latches & Registers

9. Consider the cascade of two one-bit registers shown below. Show the output waveforms at points A and B for the input waveform provided below. Assume both A and B begin at 0.

Ans