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Main points of this past exam are: Memory Locations, Die Cost, Die Area, Cpu Chip, Chip Cost, Dominant Cost, Mips-Like Program,, Stack Machine, Short Program, Memory Machine
Typology: Exams
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University of California, Berkeley College of Engineering Computer Science Division | EECS
Spring 1998 J. Wawrzynek
CS152 Computer Architecture and Engineering Midterm I
(a) [1 p oints] True or False. Die cost is prop ortional to die area 2 :
(b) [1 p oints] True or False. CPU chip cost is the dominant cost in workstation system hardware cost:
(c) [1 p oints] What instruction is used for subtract immediate on the MIPS?
(d) [1 p oints] How would you execute a NOP op eration on a MIPS pro cessor?
(e) [1 p oints] The MIPS uses register 31 for a \link register" in function calls. What instruction is used for \return"?
(f ) [2 p oints] In 20 words or less, explain why the JAVA virtual machine is a stack based architecture.
(g) [2 p oints] A carry-lo okahead adder can complete an N-bit add in time prop ortional to log(N) and requires a numb er of gates prop ortional to (cho ose one): log(N), N, N^2.
(h) [1 p oints] Given the following MIPS-like program, with memory lo cations a,b, and c:
lw r1,a lw r2,b add r3,r1,r sw r3,c
Write the same program for a stack machine:
(i) [1 p oints] Write a short program for a memory{memory machine for the same op eration:
(a) 12-bit instructions and 12-bit datawords. (b) Word addressing (memory address refer to words not bytes). (c) A single instruction format, with two register sp eci ers, and no immediates:
OPCODE (4 bits) RA (4 bits) RB (4 bits)
(d) 16 general purp ose registers. (e) The following set of instructions:
Instruction Name RTL description Arithmetic Add ADD RA,RB Reg le[RA] Reg le[RA] + Reg le[RB] Arithmetic Sub SUB RA,RB Reg le[RA] Reg le[RA] - Reg le[RB] Logical OR OR RA,RB Reg le[RA] Reg le[RA] OR Reg le[RB] Load word LDW RA,RB Reg le[RA] DataMemory[RB] Store word STW RA,RB DataMemory[RB] Reg le[RA] Branch if Equal Zero BEQ RA,RB IF Reg le[RA] == 0 THEN PC Reg le[RB]
Your task is to design a single cycle pro cessor.
(a) Sp ecify the typ e of comp onents that you will need to build the datapath. Draw a symb ol for each typ e and clearly lab el the inputs and outputs of each. Give each a name to signify its function.
(b) Connect the comp onents into a datapath and draw all connections. Clearly lab el all the control signals and list them again b elow your datapath. Don't forget the program counter. Do not design the controller.
Control signals:
Y
A B
(a) In the circuit shown b elow, what is the delay from input x 1 to y , assuming that all inputs are stable at time t = 0? In this part and the other parts b elow, ignore delay due to wires.
y
x
x
x2 x3 x4 x5 x
(b) Supp ose we construct a new gate, XOR, as follows:
AB Y
Fill in the table to de ne its slop e{intercept delay mo del:
Mo del Parameter Value A input capacitance B input capacitance Internal Delay Output Slop e
(c) In the circuit shown b elow using our new gate, what is the delay from input x 1 to y , assuming that all inputs are stable at time t = 0?
y
x
x
x2 x3 x4 x5 x
Recall that in class we lo oked at two designs for unsigned N-bit multiplication. The rst design works without a clo ck signal and uses N^2 full-adder cells, organized as N N-bit adders. This is called an array multiplier or a combinatorial multiplier. The second multiplier design uses N full-adder cells, organized as an N-bit adder, and takes N clo ck cycles. This design, called a shift and add multiplier, reuses the N-bit adder N times to arrive at the result. Temp orary results and op erands are stored in registers (some with the ability to shift). Consider the design of a third typ e of multiplier. This one uses only one full-adder cell, organized as a 1-bit adder and takes N^2 clo ck cycles to multiply 2 N-bit unsigned integers.
(a) Draw a blo ck diagram for such a design using the following building blo cks: shift registers , 1 full-adder cell, 1 or more ip- ops, and any simple logic gates you may need. The shift registers can b e of any size needed, can shift in either direction, have all internal bits available as outputs, and can accept a new bit to b e shifted in. You may assume that shift registers are automatically initialized with any value you want, but state these assumptions in part b). There are many ways to design this multiplier, but more credit will b e given to simplier designs and those that try to minimize the amount of state needed. Draw the multiplier on the back of another page rst and the transfer your nal drawing to the answer space. Draw neatly!
