CMP3006 Embedded Systems Programming Lecture 6: Timers & Timer Interrupts, Lecture notes of Embedded Systems

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CMP

EMBEDDED

SYSTEMS

PROGRAMMING

LECTURE 6 TIMERS & TIMER

INTERRUPTS

Atmega 328 Pinout

AVR Architecture

Timers

TIMER0 (8 bits) connected to pins 5, 6

TIMER1 (16 bits) connected to pins 9, 10

TIMER2 (8 bits) connected to pins 3, 11

Why do we need timers/counters? Why don’t

we use CPU?

They are separate hardware, does not use CPU

They are not affected by other interrupts

int main ( ) { byte counter; while (1){ counter++; } return 0; }

inefficient timer/counter

TERMINOLOGY

Frequency ()

Period ()

Duty Cycle ()

PHASE

ON

OFF

𝑇 𝐷

A FLIP-FLOP AND A COUNTER

ATmega328P Timer/Counter

Asynchronous (ripple) counter

 (^) a collection of flip-flops with the clock input of stage n connected to the output of stage n -

A generic timer/counter

Counting

Delay generating

Wave-form generating

Capturing event with timestamp

Counter register

External

source

Oscillator

Counter/Timer

COUT

Flag

16Mhz

Timer Terms

Timer0 Timer1 Timer

BOTTOM 0 0 0

MAX 255 65535 255

TOP 255/OCR0A 65535/OCR1A/ICR1 255/OCR2A

Timer Modes (Wave Generation Modes)

Normal Mode

Count up from BOTTOM to MAX

No output generated on the pins

Clear on Compare Match (CTC)

Count up from BOTTOM to TOP

Fast PWM

Count up from BOTTOM to TOP

Phase Correct PWM Mode

Count up from BOTTOM to TOP then count down to BOTTOM

Phase correct mode 0xFF TCNT 0 TOV time

TOV0: 01

FE

FF

TOV0 = 1

CTC mode TCNT 0 OCF0 OCF0 OCF time

TOV0:^0

xx

OCR0A

OCR0A

OCF0A: 01

0xFF

Timing with Prescaling Prescaling f/

Timer Registers in AVR

TCNTn (Timer/Counter register)

TOVn (Timer Overflow flag)

TCCRn (Timer Counter control register)

TIMSKn (Interrupt Mask Register)

TIFRn (Interrupt Flag Register)

OCRn (output compare register)

OCFn (output compare match flag)

Timer0 Registers FOC 0 A FOC 0 B - - WGM 02 CS 02 CS 01 CS 00 TCCR 0 B

COM 0 A 1 COM 0 A 0 COM 0 B 1 COM 0 B 0 - - WGM 01 WGM 00 TCCR 0 A

- - - - - OCF 0 B OCF 0 A TOV 0 TIFR 0

• • • • • OCIE 0 B OCIE 0 A TOI 0 E^ TIMSK

D 7 D 0

TIMSK 0 :

• • • • OCIE 1 B OCIE 1 A TOI 1 E

D 7 D 0

TIMSK 1 : (^) ICIE

• • • • • OCIE 2 B OCIE 2 A TOI 2 E

D 7 D 0

TIMSK 2 :

Timer FOC 0 A FOC 0 B - - WGM 02 CS 02 CS 01 CS 00 TCCR 0 B

COM 0 A 1 COM 0 A 0 COM^0 B^1 COM^0 B^0 -^ - WGM 01 WGM 00 TCCR 0 A

WGM02 WGM01 WGM00 TOP

0 0 0 Normal 255 0 0 1 Phase correct PWM 255 0 1 0 CTC (Clear Timer on Compare Match) OCR0A 0 1 1 Fast PWM 255 1 0 0 Reserved - 1 0 1 Phase correct PWM OCR0A 1 1 0 Reserved - 1 1 1 Fast PWM OCR0A