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UNIVERSITY OF CALIFORNIA Department of Electrical EngineeringCollege of Engineering and Computer Sciences
Professor Oldham Fall 1999
EECS 40 — MIDTERM
10 November 1999
Name: ______________________________ Student ID: _________
Last, First
TA: o Kusuma
o Chang
Guidelines:
1. Closed book and notes except 1 page of formulas.
2. You may use a calculator.
3. Do not unstaple the exam.
4. Show all your work and reasoning on the exam in order to receive full or partial credit.
5. This exam contains 12 pages plus the cover page and 2 sheets of scratch paper included at the end of the
exam. You can remove these from the rest of the exam if you wish.
Problem
Points Possible
Your Score
Total 100
K = 10 3
m = 10 –^3 μ = 10 –^6 n = 10 –^9 p = 10 –^12 f = 10 –^15
Problem 1 (20 points)
What is the value of the unknown node voltage in each of the following circuits? Assume diodes are perfect rec-
tifiers.
(a)
(b)
(c)
(d)
(e)
(f) A cross-section for a CMOS chip is shown on the facing page. Some node voltages are indicated. Please tell
us what the values are for the node voltages at nodes U, W, R, S.
5V 6V
10V 9V
X
100K V
X = ____________________
100K
Y 12V
V (^) Y = ____________________
100K
Z 25V V (^) Z =____________________
100K
A
B
−+
V AB = ____________________
77V
100K
C
V CD = ____________________
D
77V
V W = _______________
V U = _______________
V R = _______________
V S =_______________
Problem 2 (20 points)
Shown on the opposite page is the layout and two cross-sections through a CMOS inverter. A list of components
follows. You are to indicate, by labelling, the location of that feature on the figure. The first question is used as an
example.
2.1 Layout
(1) A contact to polysilicon [EXAMPLE]
(2) gate of NMOS transistor
(3) the W dimension of the PMOS transistor
(4) contact to p-type substrate
(5) metal contact to PMOS gate
(6) spacing from n+ source gain areas to well mask
(7) input electrode
(8) output electrode
2.3 Masks
A possible list of masks for this process follows. You are to order the masks by simply filling in the mask num-
ber. It is possible that one or more masks is missing. If so, you must fill out a new mask row for each missing
mask.
2.4 Gate delay
For this layout, what do we expect for the relationship between gate delay for output rising (t pLH ), and output
falling (t pHL )? Answer by putting in the correct symbol in the box (=, >, or <).
MASK# NAME FUNCTION
Poly Define polysilicon areas N-select Define n+ implant areas P-select Define p+ implant areas Oxide Define areas for gate oxide Metal Define metal conductor pattern
Why? __________________________________________________________________________
t pLH tpHL
Put symbol here
2.2 Cross-sections
(a) well region
(b) field oxide
(c) NMOS gate oxide
(d) metal contact to PMOS source or drain
(e) poly on field oxide
(f) metal over field oxide
(g) contact to NMOS source or drain
(h) oxide over polysilicon gate
Fill in mask
here
Prob. 2 – Schematic for CMOS Inverter
Problem 3 Answer Sheet
(d)
1
2
3
4
5
time
V OUT ( V)
Problem 4 (20 points)
A CMOS inverter drives an off-chip capacitance load, as shown below. All you know about the MOS transistors
is shown in the graphs. (DO NOT ASK for more information!)
(a) Draw the circuit model (in the box provided on opposite page) for the circuit (replacing transistors with
appropriate simpler elements, such as voltage sources, current sources, resistors, capacitors, inductors)
when. No numerical values are required in part (a).
(b) Suppose suddenly switches to 0V at. Draw the new circuit model in the box provided (again
with simpler elements). Show both the general form and the numerical values for all parameters.
(c) Sketch the form of versus time for to on the axes provided. (No numbers needed.)
(d) What is the time delay for to go to (in n sec)?
(e) At what time does equal 1 V (in n sec)?
V DD = 3 V
C (^) LOAD = 5 pF
V IN V^ OUT
1
3 2
1 2 3
- I (^) Dp (mA)
- V (^) GSp= 1V
- VDSp
1
3 2
1 2 3
IDn (mA)
- V (^) GS = 3V
- V (^) GS= 2V
- VGS =1V VDSn
V IN = 3V
V (^) IN t = 0 +
V (^) OUT t = 0 + t →∞
V OUT V DD ⁄ 2
∆t = ____________________nsec
V OUT
t =___________________nsec
Problem 5 (20 points)
(a) You open up your Robot Kit and find the following circuit. You suspect it is a linear voltage amplifier. You
know the differential amplifier has very high internal gain.
(a.1) Is it a linear amplifier?
(a.2) If so, what is the voltage gain? [If not, ignore (a.2).]
(a.3) If not, why not?
(b) You also find the following circuit. Again you suspect a linear amplifier. You know the differential ampli-
fier has very high internal gain.
(b.1) Is it a linear amplifier?
(b.2) If so, what is the voltage gain? [If not, ignore (b.2).]
(b.3) If not, why not?
(c) Carefully sketch the curve of versus for circuit (a) on the graph axes provided for
(d) Carefully sketch the curve of versus for circuit (b) on the graph axes provided for
V (^) o ------V (^) i-
V (^) i
10K
+Rail = +5.2V −Rail = 0 V
speaker
190K
33.3KΩ
Linear amplifier? ______________________
A (^) V VV^ o i
≡ -------= ____________________
V (^) o (Yes or No)
+ − 0 to +250 mVsignal
If not, why not? ______________________
+Rail = +5.2V −Rail = 0 V
signal
10K
0.2V
Vo
Linear amplifier?______________________
A (^) V VV^ o i
≡ ------- =____________________
500K Vi
0 to +250 mV (Yes or No)
If not, why not?______________________
V OUT V IN
0 ≤ V (^) i ≤250mV
V OUT V IN
0 ≤ V (^) i ≤250mV
Prob. 5. Answer Sheet
(c)
(d)
50 100 150 200
1
2
3
4
5
6
V (^) IN ( mV)
V OUT ( V)
250
50 100 150 200
1
2
3
4
5
6
V (^) IN ( mV)
V OUT ( V)
250
