COMPUTER ORGANIZATION, Study notes of Digital Electronics

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Dept., of C.S.E, RCEW(3T),KNL. R

B.TECH II-II SEM. COMPUTER ORGANIZATION (15A05402)

MEMORY SYSTEMUNIT 3

3.1 BASIC CONCEPTS The maximum size of the memory that can be used in any computer is determined by the addressing scheme. For example, a 16-bit computer that generates 16-bit addresses is capable of addressing upto 2 access upto 2^16 =64K memory locations. If a machine generates 32 (^32) = 4G memory locations. This number represents the size of address-bit addresses, it can space of the computer. Address 16 Bit (^) 2 Memory Locations (^16) = 64 K 32 Bit 40 Bit 226432 = 4G (Giga)= IT (Tera) called word computer is called byte^ If the smallest addressable unit of information is a memory word, the machine is-addressable. If individual memory bytes are assigned distinct addresses, the-addressable. Most of the commercial machines are byte- addressable. For example in a byte contains 4 bytes. A possible word-address assignment would be:-addressable 32-bit computer, each memory word Word Address 0 Byte Address 0 1 2 3 (^48 48 59 106 )

.. …..….. With the above structure a READ or WRITE may involve an entire memory word^.^ ….. or it may involve only a byte. In the case of byte read, other bytes can also be read but ignored by the CPU. However, during a write cycle, the control circuitry of the MM must ensure t specify the word and the lowerhat only the specified byte is altered. In this case, the higher-order 2 bits can specify the byte within the word.-order 30 bits can

Memory Cycle Time : It is an important measure of the memory system. It is the minimum time delay - required between the initiations of two successive memory operations (for example, the time between two successive READ operations). The cycle time is usually slightly longer than the access time. RANDOM ACCESS MEMORY (RAM): for a READ or WRITE operation in some f^ A memory unit is called a Random Access Memory if any location can be accessedixed amount of time that is independent of the location’s address. Main memory units are of this type. This distinguishes them from serial or partly serial access storage devices such as magnetic tapes and disks which are used as the secondary storage devi Cache Memory:- ce. can be fetched from compatibly priced main memory unit. Thus the memory cycle time^ The CPU of a computer can usually process instructions and data faster than they become the bottleneck in the system. One way to reduce the memory access use cache memory. This is a small and fast memory that is inserted between the larger, time is to slower main memory and the CPU. This holds the currently active segments of a program and its data. Because of the locality of address references, the CPU ca time, find the relevant information in the cache memory itself (cachen, most of the hit) and infrequently needs access to the main memory (cache miss) with suitable size of the cache memory, cache hit rates of over 90% are possible leading to a cost-effective increase in the performance of the system. Memory Interleaving: and arranges addressing so that successive words in the address space are placed in This technique divides the memory system into a number of memory modules - different modules. When the access will be to different modules. Since parallel access to these modules is requests for memory access involve consecutive addresses, possible, the average rate of fetching words from the Main Memory can be increased. Virtual Memory: In a virtual - memory System, the address generated by the CPU is referred to as a virtual or logical address. The corresponding physical address can be different and the required mapping is implemented by a special memory control unit, often called the memory management program execution according to system requirements. unit. The mapping function itself may be changed during

the physical address space; while the former can be as large as thBecause of the distinction made between the logical (virtual) address space ande addressing capability of the CPU, the actual physical memory can be much smaller. Only the active portion of the virtual address space is mapped onto the physical memory and the rest of the virtual address space is mapped onto the bulk storage device use addressed information is in the Main Memory (MM), it is accessed and execution proceeds. Otherwise, an exception is generated, in response to which the memoryd. If the management unit transfers a contigious block of words containing the desired word from the bulk storage unit to the MM, displacing some block that is currently inactive. If the memory is managed in such a way that, such transfers are required relatively infrequency (ie the CPU will generally find the required information in the MM), the virt creating an illusion of a large memory with a small, in expensive MM.ual memory system can provide a reasonably good performance and succeed in INTERNAL ORGANIZATION OF MEMORY CHIPS: capable of storing one bit of information. Each row of cells constitutes a memory word^ Memory cells are usually organized in the form of array, in^ which each cell is and all cells of a row are connected to a common line called as word line. The cells in each column are connected to Sense / Write circuit by two bit the possible arrangements of memory cells. lines. Figure 3..1 shows

During a write operation, the sense / write circuit receives input information and stores^ The Sense / Write circuits are connected to data input or output lines of the chip. it in the cel circuits are connected to a single bidirectional data line that can be connected to a data bus of the cpu.ls of the selected word. The data input and data output of each sense / write R / W → specifies the required operation. CS → Chip Select input selects a given chip in the multi-chip memory system

3.3 SEMI CONDUCTOR RAM MEMORIES: time ranges from 100ns to 10ns. When first introduced Semi-Conductor memories are available is a wide range of speeds. Their cycle in the late 1960s, they were much more expensive. But now they are very cheap, and used almost exclusively in implementing main memories. 3.3.1STATIC MEMORIES: Memories that consist of circuits capable of retaining their state as long as power is applied are known as static memory. Static random bistable latching circuitry to store each bit. The term - access memory ( SRAM ) is a type of semiconductor memory that static differentiates it from dynamic uses RAM (DRAM) which must be periodically refreshed. SRAM exhibits data remanence, but is still volatile in the conventional sense that data is eventually lost when the memory is not powered. Figure 3.2 shows the implementation of static RAM.

fig: 3.2Static RAM cell

Two inverters are cross connected to form a latch. The latch is connected to two bit lines by transistors T 1 and T 2. These transistors act as switches that can be opened / closed under the control of the word line. When the word line is at ground level, the transistors are turned off and the latch retains its state. Read Operation: In order to read the state of the SRAM cell, the word line is ac and T tivated to close switches T 1 b is low. Thus b and b the bit line monitors the state of b a^2. If the cell is in state 1, the signal on bit line b is high and the signal on the bit lineꞌ^ are complement of each other. Sense / write circuit at the end ofnd bꞌ (^) and set the output according. Write Operation: The state of the cell is set by placing the appropriate value on bit line b and its complement on b corresponding state. The required sig circuit. ꞌ^ and then activating the word line. This forces the cell into thenal on the bit lines are generated by Sense / Write CMOS RAM CELL Transistor pairs (T 3 , T 5 ) and (T 4 , T 6 ) form the inverters in the latch. In state 1, the voltage at point X is high by having T (Closed), bit line b and bꞌ (^) will have high and low signals respectively. The CMOS requires 5 , T 6 on and T 4 , T 5 are OFF. Thus T 1 and T 2 returned ON 5V (in older version) or 3.3.V (in new version) of power supply voltage.

Figure3.3 : CMOS cell (Complementary Metal oxide Semi-Conductor):

If charge on capacitor < threshold value During a read operation, the transistor is turned on and a sense amplifier → Bit line will set to logic value 0. connected to the bit line detects whether the charge on the capacitor is above the threshold value. A 16-megabit DRAM chip configured as 2M x 8, is show n in Figure 3.5.

Figure 3.5: Internal organization of a 2M X 8 dynamic Memory chip. DESCRIPTION needed to access a byte in the memory (12 bit to select a row, and 9 bits specify the The 4 bit cells in each row are divided into 512 groups of 8. 21 bit address is : group of 8 bits in the selected row). A (0-8) → Row address of a byte. During Read/ Write operation, the row address is applied first. It is loaded into the row^ A (9-20)^ → Column^ address of a byte. address latch in response to a signal pulse on Row Address Strobe (RAS) input of the chip. When a Read operation is initiated, all cells on the se refreshed. Shortly after the row address is loaded, the column address is applied to thelected row are read and address pins and loaded into Column Address Strobe (CAS). The information in this latch is decoded and the appropriate group of 8 Sense/Write circuits is selected. R/W =1(read

The output values of the selected circuits are transferred to the data lines D0 R/W=0 (write operation). The information on D0 circuits. - D7 is transferred to the selected - D7. RAS and CAS are active low so that they from high to low. This is because they are indicated by RAS and CAS. To ensure that the cause the latching of address when they change contents of a DRAM‘s are maintained, each row of cells must be accessed periodically. Refresh operation usually perform t controller circuit provides the necessary control signals RAS and CAS that govern thehis function automatically. A specialized memory timing. The processor must take into account the delay in the response of the memory. Such memories are referred to as Asynchronous DRAM‘s. Fast Page Mode: Transferring the bytes in sequential order is achieved by applying the consecutive sequence of column address under the control of successive CAS signals. This scheme allows transferring a block of data at a faster rate. called as Fast Page Mode. The block of transfer capability is Synchronous DRAM: Here the operations are directly synchronized with clock signal. The address and data connections are buffered by means of registers. The output of each sense amplifier is connected to a latch. A Read operation causes the contents of all cells in the selected row to be loaded in these latches. The Figure 3.6 shows the structure of SDRAM.

Figure 3.6: Synchronous DRAM

Double Data Rate SDRAM (DDR The double data rate SDRAM transfer data on The standard SDRAM performs all actions on the rising edge of the clock signal. - SDRAM): both the edges (loading edge, trailing edge). The Bandwidth of DDR possible to access the data at high rate, the cell array is organized into two banks. Each-SDRAM is doubled for long burst transfer. To make it bank can be accessed separately. Consecutive different banks. Such interleaving of words allows simultaneous access to two words that are transferred on successive edge of the clock. words of a given block are stored in 3.3.2 La The physical implementatio rger Memories: Dynamic Memory System: n is done in the form of Memory Modules. If a large memory is built by placing DRAM chips directly on the main system printed circuit board that contains the processor, often referred to as Motherboard; it will occupy large amount development of larger memory units known as SIMM‘s and DIMM‘s of space on the board. These packaging consideration have led to the SIMM DIMM-- Single Inline memory ModuleDual Inline memory Module

MEMORY SYSTEM CONSIDERATION: address inputs. The address is divided into two parts. They are, To reduce the number of pins, the dynamic memory chips use multiplexed High Order Address Bit into memory chips under the c (Select a row in cell array and it is provided first andontrol of RAS signal). latched Low Order Address Bit pins and latched using CAS signals). The Multiplexing of address bit is usually done by Memory Controller Circuit, as (Selects a column and they are provided on same address shown in Figure 3.8.

Figure 3.8: Use of Memory Controller the control of a request signal which indicates that a memory access operation is^ The Controller accepts a complete address and R/W signal from the processor, under needed. The Controller then forwards the row and colu memory and generates RAS and CAS signals. It also sends R/W and CS signals to themn portions of the address to the memory. The CS signal is usually active low, hence it is shown as CS. Refresh Overhead: rows is 16ms whereas 64ms in SDRAM.^ All dynamic memories have to be refreshed. In DRAM,^ the period for refreshing all Rambus Memory: The usage of wide bus is expensive. Rambus developed the implementation of

At Logic value ‗0‘ → Transistor (T) is connected to the ground point (P). Transistor switch Figure 3.9: ROM cell is closed and voltage on bit line nearly drops to zero. At Logic value ‗1‘ → Transistor switch is open. The bit line remains at high voltage. To read the state of the cell, the word line is activated. A Sense circuit at the end of the bit line generates the proper output value. Different types of non-volatile memory are:

• • PROEPROMM
• • EEPROMFlash Memory PROM: Programmable ROM: PROM allows the data to be loaded by the user. Programmability is achieved by inserting a fuse at point P in a ROM cell. Before it is programmed, the memory contains all 0‘s. The user can insert 1‘s at t locations using high current pulse. This process is irreversible.he required location by burning out the fuse at these Merit: • It provides flexibility.
• • It is faster.It is less expensive because they can be programmed directly by the user. EPROM EPROM allows the stored data to be erased and new data to be loaded. In an - Erasable reprogrammable ROM: EPROM cell, a connection to ground is always made at used, which has the ability to function either as a normal transist ‗P‘ and a special transistor isor or as a disabled transistor that is always turned off. This transistor can be programmed to behave as a

permanently open switch, by injecting charge into it that becomes trapped inside. Erasure requires dissipating the charges trapped in the transistor of memory cells. This can be done by exposing the chip to ultraviolet light, so that EPROM chips are mounted in packages that have transparent windows. Merits: • • It provides flexibility during the development phase of digital system.It is capable of retaining the stored information for a long time. Demerits: • The chip must be physically removed from the circuit for reprogramming and its entire contents are erased by UV light. EEPROM: EEPROM- Electrically Erasable ROM: (also written E (^2) PROM and pronounced "e-e-prom," "double-e prom," "e O nly-squared," or simply "e M emory and is a type of non-prom") stands for-volatile memory used in computers and other E lectrically E rasable P rogrammable R ead- electronic devices to store small amounts of data that removed, e.g., calibration tables or device configuration. must be saved when power is When larger amounts of static data are to be stored (such as in USB flash drives) a specific type of EEPROM such as flash memory is more economical than traditional EEPROM devices. EEPROMs are realized as arrays of floating-gate transistors. EEPROM is user modifiable read only memory (ROM) that can be erased and reprogrammed (written to) repeatedly through the application of higher than normal electrical voltage generate EPROM usually must be removed from the device for erasing and programming, whereas EEPROMs can be programmed and erased in circuit. Originally, EEPROMs were limited tod externally or internally in the case of modern EEPROMs. single byte operations which page operations. It also has a limited life made them slower, but modern EEPROMs allow multi - that is, the number of times it could be-byte reprogrammed was limited to tens or hundreds of thousands of times. That limitation has been extended to a million write operations in modern EEPROMs. In an EEPROM that is frequently reprogrammed while the computer is in use, the life of the EEPROM can be an important design consideration. It is for this reason that EEPROMs were used for configuration information, rather than random access memory. Merits: It can be both programmed and erased electrically. Demerits:^ It allows the erasing of all cell contents selectively. It requires different voltage for erasing, writing and reading the stored data.

SPEED, SIZE COST:

Magnetic Disk: A huge amount of cost effective storage can be provided by magnetic disk. The main memory can be built with DRAM which leaves SRA‘s to be used in smaller units where speed is of essence.

3.5 MEMORY HIERARCHY

To this point system as a CPU that executes instructions and a memory system that holds instructions and data for the CPU. In our simple in our study of systems, we have relied on a simple model of a computer \model, the memory system is a linear array of bytes, and the effective model as far as it goes, it does not reflect the way that modern systems really CPU can access each memory location in a constant amount of time. While this is an work. In practice, a memory system is a hierarchy of storage devices with differen capacities, costs, and access times. CPU registers hold the most frequently used data. Small,t fast cache memories nearby the CPU act as staging areas for a subset of the data and instructions stored in the relatively slow main memory.

The main memo staging areas for data stored on the disks or tapes of other machines connected byry stages data stored on large, slow disks, which in turn often serve as networks. Memory hierarchies work because well written programs tend to access the storage at any pa So the storage at the next level can be slower, and thus larger and cheaper per bit. The overall effect is a large pool of memory that costs as much as the cheap storage nrticular level more frequently than they access the storage at the next lower level.ear the bottom of the hierarchy, but that serves data to programs at the rate of the fast storage near the top of the hierarchy. As a programmer, you need to understand the memory hierarchy because it has a big impact on the performance of your applications. If the data your program needs are stored in a CPU register, then they can be accessed in zero cycles during the execution of the instruction. If stored in a cache, 1 to 30 cycles. If stored in main memory, 50 to 200 cycles. realized as the hierarchy shown in the Figure 14.10.^ And if stored in disk tens^ of millions of cycles!. The entire computer memory can be Here, then, is a fundamental and enduring idea in computer systems: If you understand how the system moves data up and down the memory hierarchy, then you can write your application programs so that their data items are stored higher in the hierarchy, where the CPU can access them more quickly. This idea centers on a fundamental property of computer programs known as locality. again, or they tend to access sets of nearby data items. Programs with good locality tend^ Programs with good locality tend to access the same set of data items over and over to access more data items from the upper levels of the memory hierarchy than prog with poor locality, and thus run faster. rams For example, the running times of different matrix multiplication kernels that perform thesame number of arithmetic operations, but have different degrees of locality, can vary by a factor of 20!