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COCKROFT WALTON MULTIPLIER CIRCUIT DESIGN, Lecture notes of Electrical Circuit Analysis

COCKROFT WALTON MULTIPLIER CIRCUIT DESIGN WITH PROTEUS AND THEORY ABOUT COCKROFT WALTON

Typology: Lecture notes

2018/2019

Uploaded on 12/22/2019

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Cockcroft–Walton Voltage Multiplier Simulation on Proteus
CW multiplier is basically consists of n stages of a voltage doubler. A n stages CW
converts Vpp (peak to peak) source voltage into n*Vpp or 2*n*Vp. Using only diodes
and capacitors and cascading basic block, we can convert small AC voltage into high
DC voltage. So a N stage CW voltage multiplier converts input with following way.
First of all let's analyse it fundamental building block to understand how it works.
Here source is connected to a capacitor and a diode in parallel with reverse bias
condition then there is another diode in forward bias configuration and then there is
another capacitor. This Circuit Works in a following way.
 In fist cycle of the input, _Vp, Capacitor C1 is fully charged with diode D1. Then in positive
cycle this capacitor charged up to 2Vp. Then capacitor C5 charged with diode D2 upto 2Vmax
and in next stage whole cycle repeated it self.
pf3
pf4
pf5

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Cockcroft–Walton Voltage Multiplier Simulation on Proteus

CW multiplier is basically consists of n stages of a voltage doubler. A n stages CW converts Vpp (peak to peak) source voltage into nVpp or 2n*Vp. Using only diodes and capacitors and cascading basic block, we can convert small AC voltage into high DC voltage. So a N stage CW voltage multiplier converts input with following way. First of all let's analyse it fundamental building block to understand how it works. Here source is connected to a capacitor and a diode in parallel with reverse bias condition then there is another diode in forward bias configuration and then there is another capacitor. This Circuit Works in a following way.  In fist cycle of the input, _Vp, Capacitor C1 is fully charged with diode D1. Then in positive cycle this capacitor charged up to 2Vp. Then capacitor C5 charged with diode D2 upto 2Vmax and in next stage whole cycle repeated it self.

Design of 100 kV CW with 10 kV source and 10 mA load current Now to multiply voltage by factor of 10 we have to cascade this fundamental circuit into 5 stages this way we will get 100kV with 2510kV. So number of stages = Second important thing here is capacitor values and rating. Voltage drop formula for this circuit is as follows

∆ V =

I

f C [

n = 1 n

n .2 n +∑

n = 1 n

n ]

Now this formula describes that for a n stage cascaded CW multiplier, with frequency f and load current of I with C capacitance will have voltage drop of Delta V across output. From here we can find value of capacitance for our circuit by assuming a fair value of voltage tolerance. This C also effects time constant and ripples in this multiplier. So we are supposing a del V=1V f=50Hz I=10mA So capacitance value for this case would be 20mF capacitor. Now we need to calculate ripple in this circuit. Formula for ripple calculation would be

δVV total =

I f C × ( n ( n + 1 )) 2 So in our case ripple voltage would be .15% of total voltage. Rating of the capacitors and diodes are one important parameter. As all the capacitors are stressed with 2Vmax of their stage so Capcitor and diode rating should be greater that 2Vmax of that stage which means second stage will have rating of 20kV, third will have 40 kV and it goes this way. Proteus Simulation:

Output Voltage vs Input Voltage: Output V eventually constant Load Current: Load Current curve initially have some ripples which eventually becomes zeros at the end Voltages at V n' points:

Voltages are very oscillating but are double in each stage. Voltages at V n points: Voltages at Vn points. They have less ripples at quite stable. Also they are double on each stage