Cmos digital integrated circuit, Thesis of Very large scale integration (VLSI)

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Physical and Materials Constants

Boltzmann's constant

Electron charge

Thermal voltage

Energy gap of silicon (Si)

Intrinsic carrier

concentration of silicon (Si)

Dielectric constant

of vacuum

Dielectric constant

of silicon (Si)

kT/q 0. (at T= 300 K)

Eg 1.

(at T = 300 K)

ni 1.45 x 1010

(at T = 300 K)

60 8.85 x 10-

ESi 11.7 x O

Dielectric constant of silicon dioxide (SiO 2 )

Commonly Used Prefixes for Units

giga mega kilo milli micro nano pico femto

k

q

1.38 x 10-23 J/K

1.6 x 10-19 C

V

eV

cm7^3

F/cm

F/cm

6.x 3.97 x EO F/cm

G

M

k m In

n p f

109 106 103 10- 10- 10- 10- 10-

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CMOS DIGITAL lNTEORATEO CIRCUITS: ANALYSIS ANDD€SIGN TliJRD EDITION

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CONTENTS

8 SEQUENTIAL MOS LOGIC CIRCUITS 312 vii

• 1 INTRODUCTION PREFACE xi - 1.1 Historical Perspective - 1.2 Objective and Organization of the Book - 1.3 A Circuit Design Example
• 2 FABRICATION OF MOSFETs - 2.1 Introduction - 2.2 Fabrication Process Flow: Basic Steps - 2.3 The CMOS nWell Process - 2.4 Layout Design Rules - 2.5 Full-Custom Mask Layout Design - References - Exercise Problems
• 3 MOS TRANSISTOR - 3.1 The Metal Oxide Semiconductor (MOS) Structure - 3.2 The MOS System under External Bias - Transistor (MOSFET) 3.3 Structure and Operation of MOS - 3.4 MOSFET Current-Voltage Characteristics - 3.5 MOSFET Scaling and Small-Geometry Effects - 3.6 MOSFET Capacitances - References - Exercise Problems - USING SPICE vi. 4 MODELING OF MOS TRANSISTORS - 4.1 Basic Concepts Contents - 4.2 The LEVEL 1 Model Equations - 4.3 The LEVEL 2 Model Equations - 4.4 The LEVEL 3 Model Equations - 4.5 Capacitance Models - 4.6 Comparison of the SPICE MOSFET Models - References - Appendix: Typical SPICE Model Parameters - Exercise Problems
• 5 MOS INVERTERS: STATIC CHARACTERISTICS - 5.1 Introduction - 5.2 Resistive-Load Inverter - 5.3 Inverters with n-Type MOSFET Load - 5.5 CMOS Inverter - References - Exercise Problems - AND INTERCONNECT EFFECTS 6 MOS INVERTERS: SWITCHING CHARACTERISTICS - 6.1 Introduction - 6.2 Delay-Time Definitions - 6.3 Calculation of Delay Times - 6.4 Inverter Design with Delay Constraints - 6.5 Estimation of Interconnect Parasitics - 6.6 Calculation of Interconnect Delay - 6.7 Switching Power Dissipation of CMOS Inverters - References - Appendix: Super Buffer Design - Exercise Problems
  • 7 COMBINATIONAL MOS LOGIC CIRCUITS - 7.1 Introduction - 7.2 MOS Logic Circuits with Depletion nMOS Loads - 7.3 CMOS Logic Circuits - 7.4 Complex Logic Circuits - 7.5 CMOS Transmission Gates (Pass Gates) - References - Exercise Problems - 8.2 Behavior of Bistable Elements 8.1 Introduction 312 Contents - 8.3 The SR Latch Circuit - 8.4 Clocked Latch and Flip-Flop Circuits - 8.5 CMOS D-Latch and Edge-Triggered Flip-Flop - Appendix: Schmitt Trigger Circuit - Exercise Problems
    • 9 DYNAMIC LOGIC CIRCUITS - 9.1 Introduction - 9.2 Basic Principles of Pass Transistor Circuits - 9.3 Voltage Bootstrapping - 9.4 Synchronous Dynamic Circuit Techniques - 9.5 High-Performance Dynamic CMOS Circuits - References - Exercise Problems
    • 10 SEMICONDUCTOR MEMORIES - 10.1 Introduction - 10.2 Read-Only Memory (ROM) Circuits - 10.3 Static Read-Write Memory (SRAM) Circuits - 10.4 Dynamic Read-Write Memory (DRAM) Circuits - References - Exercise Problems
  • 11 LOW-POWER CMOS LOGIC CIRCUITS - 11.1 Introduction - 11.2 Overview of Power Consumption - 11.3 Low-Power Design Through Voltage Scaling - 11.4 Estimation and Optimization of Switching Activity - 11.5 Reduction of Switched Capacitance - 11.6 Adiabatic Logic Circuits - References - Exercise Problems
• 12 BiCMOS LOGIC CIRCUITS - 12.1 Introduction - Structure and Operation 12.2 Bipolar Junction Transistor (BJT):
• viii 12.3 Dynamic Behavior of BJTs - 12.4 Basic BiCMOS Circuits: Static Behavior
• Contents 12.5 Switching Delay in BiCMOS Logic Circuits - 12.6 BiCMOS Applications - References - Exercise Problems
  • 13 CHIP INPUT AND OUTPUT (O) CIRCUITS - 13.1 Introduction - 13.2 ESD Protection - 13.3 Input Circuits - 13.4 Output Circuits and L(di/dt) Noise - 13.5 On-Chip Clock Generation and Distribution - 13.6 Latch-Up and Its Prevention - References - Exercise Problems
  • 14 VLSI DESIGN METHODOLOGIES - 14.1 Introduction - 14.2 VLSI Design Flow - 14.3 Design Hierarchy - 14.4 Concepts of Regularity, Modularity and Locality - 14.5 VLSI Design Styles - 14.6 Design Quality - 14.7 Packaging Technology - 14.8 Computer-Aided Design Technology - References - Exercise Problems
    • 15 DESIGN FOR MANUFACTURABILITY - 15.1 Introduction - 15.2 Process Variations - 15.3 Basic Concepts and Definitions - 15.4 Design of Experiments and Performance Modeling - 15.5 Parametric Yield Estimation - 15.6 Parametric Yield Maximization - 15.7 Worst-Case Analysis - 15.8 Performance Variability Minimization - References - Exercise Problems

ABOUT THE^ AUTIORS

Sung-Mo (Steve) Kang received the Ph.D. degree in electrical engineering from^ the

University of California at Berkeley. He has worked on CMOS VLSI design at AT&T

Bell Laboratories at Murray Hill, N.J. as supervisor and member^ of^ technical^ staff of

high-end CMOS VLSI microprocessor design. Currently, he^ is^ professor^ and^ head^ of^ the department of electrical and computer engineering at the University of^ Illinois^ at^ Urbana- Champaign. He was the founding editor-in-chief of the IEEE Transactions^ on^ Very^ Large Scale Integration (VLSI) Systems^ and^ has^ served^ on^ editorial boards^ of^ several^ IEEE^ and international journals. He has received a Humboldt Research Award for Senior US Scientists, IEEE Graduate Teaching Technical Field Award, IEEE Circuits and Systems Society Technical Achievement Award, SRC Inventor Recognition Awards, IEEE CAS Darlington Prize Paper^ Award^ and^ other^ best^ paper^ awards.^ He^ has^ also^ co-authored DesignAutomationforTiming-DrivenLayout Synthesis, Hot- CarrierReliabilityofMOS VLSI Circuits, Physical Design for Multichip Modules,^ and^ Modeling^ of^ Electrical Overtstress in^ Integrated^ Circuits^ from Kluwer^ Academic^ Publishers,^ and^ Computer- Aided Design of Optoelectronic Integrated Circuits and Systems from Prentice Hall.

Yusuf Leblebici received the Ph.D. degree in electrical and computer engineering from the^ University^ of^ Illinois^ at^ Urbana-Champaign.^ He^ was^ a^ visiting^ assistant professor of^ electrical^ and^ computer^ engineering at^ the^ University^ of^ Illinois^ at^ Urbana- Champaign, associate professor of electrical and^ electronics^ engineering^ at^ Istanbul Technical University, and invited professor of^ electrical^ engineering^ at^ the^ Swiss Federal Institute of Technology in Lausanne, Switzerland. Currently,^ he^ is^ an^ associate professor of electrical and computer engineering at^ Worcester Polytechnic^ Institute. Dr. Leblebici is also a member of technical staff^ at^ the^ New^ England^ Center^ for Analog and Digital Integrated Circuit Design. His^ research^ interests^ include^ high- performance digital integrated circuit architectures, modeling and^ simulation^ of^ semi- conductor devices, computer-aided design^ of^ VLSI^ circuits, and^ VLSI^ reliability^ analy- sis. He has received a NATO Science Fellowship Award, has been^ an^ Horiors^ Scholar of the Turkish Scientific and Technological Research Council, and^ has^ received^ the Young Scientist Award of the same council. Dr. Leblebici has co-authored^ about^ fifty technical papers and two books.

PREFACE

Complementary metal oxide semiconductor (CMOS) digital integrated circuits are the

enabling technology for the modern information age. Because of their intrinsic features

in low-power consumption, large noise margins, and ease of design, CMOS integrated

circuits have been widely used to develop random access memory (RAM) chips,

microprocessor chips, digital signal processor (DSP) chips, and application- specific

integrated circuit (ASIC) chips. The popular use of CMOS circuits will grow with the

increasing demands for low-power, low-noise integrated electronic systems in the

development of portable computers, personal digital assistants (PDAs), portable phones,

and multimedia agents.

Since the field of CMOS integrated circuits alone is very broad, it is conventionally

divided into digital CMOS circuits and analog CMOS circuits. This book is focused on

the CMOS digital integrated circuits. At the University of Illinois at Urbana-Champaign,

we have tried some of the available textbooks on digital MOS integrated circuits for our

senior-level technical elective course, ECE382 - Large!Scale IntegratedCircuitDesign.

Students and instructors alike realized, however, that-there was a need for a new book with

more comprehensive treatment of CMOS digital circuits. Thus, our textbook project was

initiated several years ago by assembling our own lecture notes. Since 1993, we have used

evolving versions of this material at the University of Illinois at Urbana-Champaign, at

Istanbul Technical University and at the Swiss Federal Institute of Technology in

Lausanne. Both authors were very much encouraged by comments from their students,

colleagues, and reviewers. The first edition of CMOS Digital Integrated Circuits:

Analysis and Design was published in late 1995.

important topics of design for manufacturability and design for testability are covered in xiii

Chapters 15 and 16, respectively,

The authors have long debated the coverage of nMOS circuits in this book. We have Preface

finally concluded that some coverage should be provided for pedagogical reasons.

Studying nMOS circuits will better prepare readers for analysis of other field effect

transistor (FET) circuits such as GaAs circuits, the topology of which is quite similar to

that of depletion-load riMOS circuits. Thus, to emphasize the load concept, which is still

widely used in many areas in digital circuit design, we present basic depletion-load

nMOS circuits along with their CMOS counterparts in several places throughout the

book.

Although an immense amount of effort and attention to detail were expended to

prepare the camera-ready manuscript, this book may still have some flaws and mistakes

due to erring human nature. The authors would welcome and greatly appreciate sugges-

tions and corrections from the readers, for the improvement of the technical content as

well as the presentation style.

Acknowledgements (^) for the First Edition

Our colleagues have provided many constructive comments and encouragement for the

completion of the first edition. Professor Timothy N. Trick, former head of the depart-

ment f electrical and computer engineering at the University of Illinois at Urbana-

Champaign, has strongly supported our efforts from the very beginning. The appointment

of Sung-Mo Kang as an associate in the Center for Advanced Study at the University of

Illinois at Urbana-Champaign helped to start the process.

Yusuf Leblebici acknowledges the full support and encouragement from the depart-

ment of electrical and electronics engineering at Istanbul Technical University, where he

introduced a new digital integrated circuits course based on the early version of this book

and received very valuable feedback from his students. Yusuf Leblebici also thanks the

ETA Advanced Electronics Technologies Research and Development Foundation at

Istanbul Technical University for their generous support.

Professor Elyse Rosenbaum and Professor Resve Saleh used the early versions of the

manuscript as the textbook for ECE382 at Illinois and provided many helpful comments

and corrections which have been fully incorporated with deep appreciation. Professor

Elizabeth Brauer, currently at Northern Arizona University, has also done the same at the

University of Kentucky.

The authors would like to express sincere gratitude to Professor Janak Patel of the

University of Illinois at Urbana-Champaign for generously mentoring the authors in

writing Chapter 16, Designfor Testability. Professor Patel has provided many construc-

tive comments and many of his expert views on the subject are reflected in this chapter.

Professor Prith Banerjee of Northwestern University and Professor Farid Najm of the

University of Illinois at Urbana-Champaign also provided many good comments. We

would also like to thank Dr. Abhijit Dharchoudhury for his invaluable contribution to

Chapter 15, Designfor Manufacturability.

Professor Duran Leblebici of Istanbul Technical University, who is the father of the

second author, reviewed the entire manuscript in its early development phase, and

provided very extensive and constructive comments, many of which are reflected in the

final version. Both authors gratefully acknowledge his support during all stages of this

venture. We also thank Professor Cem Goknar of Istanbul Technical University, who

offered very detailed and valuable comments on Design for Testability, and Professor

Ugur Qilingiroglu of the same university, who offered many excellent suggestions for

improving the manuscript, especially the chapter on semiconductor memories.

Many of the authors' former and current students at the University of Illinois at

Urbana-Champaign also helped in the preparation of figures and verification of circuits

using SPICE simulations. In particular, Dr. James Morikuni, Dr. Weishi Sun, Dr. Pablo

Mena, Dr. Jaewon Kim, Mr. Steve Ho and Mr. Sueng-Yong Park deserve recognition.

Ms. Lilian Beck and the staff members of the Publications Office in the department of

electrical and computer engineering at the University of Illinois at Urbana-Champaign

read the entire manuscript and provided excellent editorial comments.

The authors would also like to thank Dr. Masakazu Shoji of AT&T Bell Laboratories,

Professor Gerold W. Neudeck of Purdue University, Professor Chin-Long Wey of

Michigan State University, Professor Andrew T. Yang of the University of Washington,

Professor Marwan M. Hassoun of Iowa State University, Professor Charles E. Stroud of

the University of Kentucky, Professor Lawrence Pileggi of the University of Texas at

Austin, and Professor Yu Hen Hu of the University of Wisconsin at Madison, who read

all or parts of the manuscript and provided many valuable comments and encouragement.

The editorial staff of McGraw-Hill has been an excellent source of strong support from

the beginning of this textbook project. The venture was originally initiated with the

enthusiastic encouragement from the previous electrical engineering editor, Ms. Anne

(Brown) Akay. Mr. George Hoffman, in spite of his relatively short association, was

extremely effective and helped settle the details of the publication planning. During the

last stage, the new electrical engineering editor, Ms. Lynn Cox, and Mr. John Morriss,

Mr. David Damstra, and Mr. Norman Pedersen of the Editing Department were superbly

effective and we enjoyed dashing with them to finish the last mile.

Acknowledgements for the Second Edition

The authors are truly indebted to many individuals who, with their efforts and their

help, made the second edition possible. We would like to thank Dr. Wolfgang Fichtner,

President and CEO of ISE Integrated Systems Engineering, Inc. and the technical staff

of ISE in Zurich, Switzerland for providing computer-generated cross-sectional color

graphics of MOS transistors and CMOS inverters, which are featured in the color

plates. The first author acknowledges the support provided by the U.S. Senior Scientist

Research Award from the Alexander von Humbold Stiftung in Germany, which was

very helpful for the second edition. The appointments of the second author as Associate

Professor at Worcester Polytechnic Institute and as Visiting Professor at the Swiss

Federal Institute of Technology in Lausanne, Switzerland have provided excellent

environments for the completion of the revision project. The second author also thanks

Professor Daniel Mlynek of the the Swiss Federal Institute of Technology in Lausanne

for his continuous encouragement and support. Many of the authors' former and current

students at the University of Illinois at Urbana-Champaign, at the Swiss Federal

Institute of Technology in Lausanne and at Worcester Polytechnic Institute also helped

in the preparation of figures and verification of circuits using SPICE simulations. In

particular, Dr. James Stroming and Mr. Frank K. Gilrkaynak deserve special recogni-

tion for their extensive and valuable efforts.

xiv

Preface

CHAPTER (^1)

INTRODUCTION

1.1. Historical Perspective

The electronics industry (^) has achieved a phenomenal growth (^) over the last few decades, mainly due to the (^) rapid advances in integration technologies (^) and large-scale systems design. The use of integrated (^) circuits in high-performance computing, (^) telecommunica- tions, and consumer electronics (^) has been growing at a very (^) fast pace. Typically, the required computational (^) and information processing power of (^) these applications is the driving force for the fast (^) development of this field. Figure 1.1 (^) gives an overview of the prominent trends in information (^) technologies over the next decade. The current leading- edge technologies (^) (such as low bit-rate video and (^) cellular communications) already provide the end-users (^) a certain amount of processing (^) power and portability. This trend is expected to continue, (^) with very important implications (^) for VLSI and systems design. One of the most (^) important characteristics of information services is their increasing need for very (^) high processing power and bandwidth (^) (in order to handle real-time video, (^) for example). (^) The other important characteristic (^) is that the information services (^) tend to become more personalized, which means that (^) the information processing devices must be more (^) intelligent and also be portable to (^) allow more mobility. This trend towards

portable, (^) distributed system architectures is (^) one of the main driving forces for system

integration, even (^) though it does not preclude a concurrent (^) and equally important trend towards (^) centralized, highly powerful information systems such as those required (^) for network computing (NC) and video services. As more and more complex functions (^) are required in various data processing (^) and telecommunications devices, the need to integrate these functions in a small (^) package is also increasing. The level of integration (^) as measured by the number of (^) logic gates in a

monolithic chip has been steadily rising for almost three decades, mainly due to the rapid

progress in processing technology and interconnect technology. Table 1.1 shows the

evolution of logic complexity in integrated circuits over the last three decades, and marks

the milestones of each era. Here, the numbers for circuit complexity should be viewed

only as representative measures to indicate the order-of-magnitude. A logic block can

contain anywhere from 10 to 100 transistors, depending on the function. State-of-the-art

ULSI chips, such as the DEC Alpha or the INTEL Pentium, contain 3 to 6 million

transistors. Note that the term VLSI has been used continuously even for chips in the

ULSI (Ultra Large Scale Integration) category, not necessarily abiding by the distinction

in Table 1.1.

I Video-on-demand I

I Speech processing/recognition |

Wireless/cellular data communication

I Data communication Multi-media applications |

I Consumer electronics]

I Personal computers I

I Portable computers |

I Network computers I

Figure 1.1. Prominent "driving" trends in information service technologies.

ERA DATE COMPLEXITY

(# of logic blocks per chip)

Single transistor 1958 < 1 Unit logic (one gate) 1960 1 Multi-function 1962 2 - 4 Complex function 1964 5 - 20 Medium Scale Integration (MSI) 1967 20 - 200 Large Scale Integration (LSI) 1972 200 - 2, Very Large Scale Integration (VLSI) 1978 2,000 - 20, Ultra Large Scale Integration (ULSI) 1989 20,000 -?

Table 1.1. Evolution of logic complexity in integrated circuits.

CHAPTER 1

I- C

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I Mainframe co

---

complexity, which was made in the early 1960s (Moore's Law). It can be observed that in terms (^) of transistor count, logic chips contain significantly fewer transistors in any given year mainly due to large consumption of chip area for complex interconnects. Memory circuits are highly regular, and thus more cells can be integrated with much less area for interconnects. This has also been one of the main reasons why the rate of increase of chip complexity (transistor count per chip) is consistently higher for memory circuits.

100 M

0 0. CD 0 U

a,

C a) 0

. E

z

10 M

1 M

100 K

10K

1 K

Year

Figure 1.3. Level of integration versus time for memory chips and logic chips.

Digital CMOS (Complementary Metal Oxide Semiconductor) integrated circuits (ICs) have been the driving 'force behind Very Large Scale Integration (VLSI) for high- performance computing and other scientific and engineering applications. The demand for digital CMOS ICs will be continually strong due to salient features such as low power, reliable performance, circuit techniques for high speed such as using dynamic circuits, and ongoing improvements in processing technology. It is now projected that the minimum feature size in CMOS (^) ICs can decrease to 0. gum within a few years. With such a technology, the level of (^) integration in a single chip can be on the order of several hundreds of millions of transistors for logic chips or even higher in the case of memory chips, which presents an immense challenge for chip developers inprocessing, design methodology, testing, and projectmanagement. (^) Through

CHAPTER 1

i the "divide-and-conquer" approach and more advanced design automation using corm- 5

puter-aided design (^) (CAD) tools, ultra-large-scale problems should be solvable. Bipolar (^) and gallium arsenide (GaAs) circuits have been used for very high (^) speed Introduction circuits, (^) and this practice may continue. (^) For instance, in Monolithic Microwave (^) Inte- grated Circuits (MMICs), GaAs (^) MESFET (MEtal Semiconductor (^) Field Effect Transis- tor) technology has been highly (^) successful. However, they are still (^) not efficient for VLSI or Ultra Large Scale Integration (ULSI) due to processing (^) difficulties and high power consumption, although for special applications their use may continue. As long as the downward scaling of (^) CMOS technology remains strong, (^) other technologies are likely to remain (^) the technology of tomorrow.

1.2. Objective and Organization of the Book

The objective of this book (^) is to help readers develop in-depth (^) analytical and design capabilities in digital CMOS (^) circuits and chips. The development (^) of VLSI chips requires an interdisciplinary (^) team of architects, logic designers, circuit and layout designers, packaging engineers, (^) test engineers, and process and (^) device engineers. Also essential are the computer (^) aids for design automation and (^) optimization. It is not possible to discuss (^) the full spectrum (^) of development issues in any (^) single book. Therefore, this book concentrates on digital circuits and also presents related (^) materials in processing and device principles essential to (^) in-depth understanding of CMOS (^) digital circuits. Often readers can become lost in (^) details and fail to see the global picture. (^) For VLSI circuit design, however, it is important (^) that the design be done in the (^) context of global optimization with proper boundary (^) conditions. In fact, the beauty of integrated (^) circuits is that the final design goal is the concerted performance of all interconnected transistors, and not of individual transistors. (^) Therefore, the interconnect issues (^) are almost as important as the issues (^) of individual transistors.-No matter (^) how well an individual transistor performs, if the technology fails to have equally good (^) interconnects, the total performance can be very poor due to large parasitic (^) capacitances and resistances; these translate into a large delay in the interconnection lines between (^) transistors or logic gates. This volume (^) is intended as a comprehensive textbook for senior-level undergradu- ate students and (^) first-year graduate students in an (^) advanced course on digital circuit design. The material presented in this book should (^) also be very useful to practicing VLSI design engineers. (^) Most of the material presented (^) has been taught over several years in undergraduate (^) and graduate-level courses in (^) the department of electrical and computer engineering (^) at the University of Illinois at Urbana-Champaign. (^) It is assumed that the readers of this book already have (^) sufficient fundamental background (^) on semiconductor (^) devices, electronic circuit design (^) and analysis, and logic theory. (^) While the interactions among logic design, (^) circuit design, and layout design (^) are strongly emphasized throughout the text, the main focus is on transistor-level circuit design and analysis. This requires a fair amount (^) of detailed current and voltage calculations, (^) as well as a good understanding of (^) how device characteristics affect overall circuit performances, such as propagation (^) delay, noise margins, and power dissipation. The relational ordering (^) and extent of the topics covered in (^) a typical digital integrated circuits course are depicted in Fig. 1.4. First, a fundamental knowledge (^) of basic device physics is required to understand (^) and use various MOSFET device models in circuit