Assignment #2 – Spring 2018 | Exercises Computer Science

Professor: Dr. Rahman

Student name:

Student Panther ID

Total&points:&80&

CDA$4101$

Assignment$#$2$–$Spring$2018$

Solution$

"""""""""""""""""""""""""""""""""""""""""""""""There!are!12!questions!in!this!assignment""""""""""""""""""""""""""""""""""""""!

Due$Date:$Friday,$2nd$March$at$11:59$PM$

• E25%$on$Saturday,$3rd$March$

• E50%$on$Sunday,$4th$March$

• Not$accepted$afterwards$

Submission$Details:$You! can! insert! your!answer! directly! in! this! Word! Document.! You!

can!also! insert!the! figure!directly! in!this! document!where!needed.!Finally,!Submit! the!PDF! of!your!

solution!in!Canvas!by!the!deadline.$

Honor$Code:$Honor!Code!This!assignment!should!be!completed!individually!to!maximize!learning.!

It! is! important! that! you! adhere! to! the! Course! Policie s,!p articularly! the! section! on! Programming!

Assignments.! Also! this!assignment! should! follow! FIU! Honor! Code! Policy.! Authorized! help! for! all!

assignments!are!limited!to!the!lab!handouts,!the!LAs,!and!the!Professor.!Copying!work!from!another!

student!or!the! Internet!is!an! honor!code!violation! as!is!giving! help!to!another! student,! which!will!

result! in! a! zero! on! the! assignment! and! possibly! further! sanctions.! Your! code! may! be! subject! to!

evaluation! by! MOSS! (Measure! of! Software! Similarity),! which! is! used! to! detect! inappropriate!

similarities!among!programs.!

Tools required: I! encourage! you! to! use! LogiSim! software.! You! may! draw! circuits! into!

LogiSim!and!insert!the!circuit!diagram!in!your!report!as!a!figure.

• You!can!download!it!from!here:!http://www.cburch.com/logisim/download.html!!

• Here is a video on how to install and use Logisim:

https://www.youtube.com/watch?v=Txp0L0lX49U

Goal: In this practice, you are going to use the basic building blocks we have learned in digital

logic to put together a basic design of a MIPS microprocessor for a simple subset of the

instruction set. These instructions illustrate most aspects of the processor:

Memory reference: lw, sw

Arithmetic/logical: add, sub, and, or, slt

Control transfer: beq, j

Combinational Elements: Remember that you can use gates (AND, OR, XOR, NOT), Adders,

ALUs, and Multiplexors as we have studied so far and as are diagrammed on the attached sheet

called combinational elements. When looking at a circuit diagram for a combinational element

we think of electricity (imagine it flowing like water) flowing from the left side of the diagram to

the right side. Each wire, represented by a single line, represents and input with electricity

flowing in at a high level (1) or a low-level (0).

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Student name: Student Panther ID Total points: 80

CDA 4101

Assignment # 2 – Spring 2018

Solution

-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐There are 12 questions in this assignment-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐-‐

Due Date: Friday, 2nd March at 11:59 PM

-‐25% on Saturday, 3 rd^ March
-‐50% on Sunday, 4 th^ March
Not accepted afterwards

Submission Details: You can insert your answer directly in this Word Document. You

can also insert the figure directly in this document where needed. Finally, Submit the PDF of your solution in Canvas by the deadline. Honor Code: Honor Code This assignment should be completed individually to maximize learning. It is important that you adhere to the Course Policies, particularly the section on Programming Assignments. Also this assignment should follow FIU Honor Code Policy. Authorized help for all assignments are limited to the lab handouts, the LAs, and the Professor. Copying work from another student or the Internet is an honor code violation as is giving help to another student, which will result in a zero on the assignment and possibly further sanctions. Your code may be subject to evaluation by MOSS (Measure of Software Similarity), which is used to detect inappropriate similarities among programs. Tools required: I encourage you to use LogiSim software. You may draw circuits into LogiSim and insert the circuit diagram in your report as a figure.

You can download it from here: http://www.cburch.com/logisim/download.html
Here is a video on how to install and use Logisim: https://www.youtube.com/watch?v=Txp0L0lX49U Goal: In this practice, you are going to use the basic building blocks we have learned in digital logic to put together a basic design of a MIPS microprocessor for a simple subset of the instruction set. These instructions illustrate most aspects of the processor: Memory reference: lw, sw Arithmetic/logical: add, sub, and, or, slt Control transfer: beq, j Combinational Elements: Remember that you can use gates (AND, OR, XOR, NOT), Adders, ALUs, and Multiplexors as we have studied so far and as are diagrammed on the attached sheet called combinational elements. When looking at a circuit diagram for a combinational element we think of electricity (imagine it flowing like water) flowing from the left side of the diagram to the right side. Each wire, represented by a single line, represents and input with electricity flowing in at a high level (1) or a low-level (0).

Student name: Student Panther ID Sequential Elements: We will also need to use something we discussed briefly earlier called a sequential element. A sequential element is one that introduces a formal sequencing into a circuit and only changes on the clock edge. The typical sequential element that we are interested in is a register. A register has an input D, and an output Q. There is always a signal on D and the goal is to have that signal reflected on Q constantly; allowing Q to change only when we are looking for that change. Consider the above diagram on sequential elements. Notice in the right figure how the value reflected on the Q output only changes on the rising edge of the clock (i.e. when the clock value goes from 0 to 1). Note that the D register shown this diagram is a one-bit register. When we are dealing with the processor design we will be using registers that are the size of a word in the machine we are designing a data path for. MIPS has 32-bit words so most of our registers and hence our “buses” or lines will be 32-bits. We can just draw a long box with a line coming in and a line coming out to represent a register of more than one bit.

Student name: Student Panther ID To continue in this exercise we will need to have one more concept down. This is the idea that we may want more than one “input” in general to a particular logic component. For example in the above diagram we may want to sometimes get a new program counter that is just the next instruction (hence the add 4 to the current program counter) or if the instruction is a branch or jump we will want to get some information from the instruction to change to the new program counter. When we want two different inputs, we need to use a multiplexor to change between the two rather than have two outputs (old PC & instruction) both going into the same input. The diagram below shows an “overview” of the whole processor design we will be modifying. P.2) [5 pt] Redo the diagram inserting multiplexors where needed. Ans.

Student name: Student Panther ID Now that you have a new diagram with multiplexors, you will be focusing on elaborating on each section of the overview diagram to account for different parts of the execution of the machine for different instructions. To make sure that you understand the overview diagram, answer the following questions with respect to it. P.3) [5 pt] What bits of the instruction will be sent to the second adder in the circuit computing the new PC – why? Ans. The second adder in the circuit computes the new PC instruction at address if a branch is taken. In this case, the program counter gets an entirely new address (new address = [PC] + 16-bit immediate from the instruction.) The 16- bit immediate in the branch instruction is first sign extended to 32 bits, shifted left 2 places and added to the current PC contents. P.4) [5 pt] What bits of the instruction will be going into each of the Register # inputs of the Register file in the center of the machine? Ans. Read Register 1 – instructions [25-21] Read Register 2 – instructions [20-16] Write Register – Instructions either [25 - 21] or [20-16], as determined by the mux. P.5) [5 pt] For what kind of instruction will the output of the data memory be going into the input of the register file? Explain. Ans. Load words instructions output data from data memory into the input of the register file. This instruction is reading a value from memory and stored in a register (bits 20-16 of the instruction). The MemtoReg and RegWrite control lines are turned on so that the value read from memory will be stored in the desired register. P.6) [5 pt] Now add to your overview picture, an oval for “control” showing lines coming in and lines going out to control the multiplexors. Label each line going into a multiplexor with a descriptive word to describe what control we want selecting the multiplexor input.

Student name: Student Panther ID Ans.

Load instructions from memeory
1. Opcode (instruction [31-26]) is fed into the control unit a. RegDst feeds MUX a high signal to tell the Register File that three register will be used b. ALUop is set to high, which signals the ALU will be utilized c. Regwrite is set to high, which signals the Register File that data will be written to a register
2. Read Register 1 is fed instructions [25-21]
3. Read Register 2 is fed instructions [20-16]
4. Write Register will be fed instructions [15-11], representing the destination register.
5. Instructions [15-0] are fed to ALU control unit to signal to the ALU what function will be computed.
6. The result is written to the register.
7. Finally the PC + 4, is passed to the PC to calculate the next instructions address. Load/Store Instructions: The load/store instructions are lw and sw. P.9) [10 pt] Now for “Load/Store” list necessary actions and draw a revised circuit diagram for the components required in the execution of a load/store instruction. Ans. Load/Store instruction use offsets to denote a memory address applied to the base address of the given register denoted as: offset(register) – 16 bits. SW 1. Load instructions from memory 2. Opcode (instruction [31-26]) is fed into the control unit a. ALUop is set to high, which signals the ALU will be utilized

Student name: Student Panther ID b. MemWrite is set to high, since the process will be writing to memory c. ALUSrc is set to high, which signals for the second ALU input

3. Instruction [25-21] contains the address where the data will be stored a. This register is read and passes its input to the ALU 4. Instruction [20-16] indicates the register that contains the data that needs to be written to memory. 5. Instruction [15- 1 1] the immediate field (offset) is extended to 32 bits and passed to the ALU to compute addition with the destination address. a. The result is used as the address that specifies to the memory unit the location to store the desired data

Increment the program counter PC+ **LW
Load instructions from memory 2.** Opcode (instruction [31-26]) is fed into the control unit a. ALUop is set to high, which signals the ALU will be utilized b. MemRead is set to high, since the process will be reading from memory c. MemtoReg is set to high, which signals that data from memory is written to a register d. Regwrite is set to high, which signals the Register File that data will be written to a register e. ALUSrc is set to high, which signals for the second ALU input 3. Instruction [25-21] contains the address where the data is stored a. This register is read and passes its input to the ALU 4. Instruction [20-16] indicates the register where the data will be stored (destination) 5. Instruction [15-11] the immediate field (offset) is extended to 32 bits and passed to the ALU to compute addition. a. The result is used as the address that specifies where memory the data is stored that will be passed to the destination register. 6. Increment the program counter PC+

Student name: Student Panther ID P.11) [5 pt] Describe how long that means this clock cycle will need to be in terms of the different instructions supported. Ans. In a single-cycle design: All instructions utilize the instruction fetch, register read and ALU operation (200ps +100ps +200ps = 500ps). A branch does not require the rest of the processor, so 500ps is its total time. A R-format instruction utilizes the register write for a total time of 600ps. A SW utilizes the Data access in addition for a total time of 700ps. A LW, is the longest instruction, because it utilizes both data access and register write for a total processing time of 800ps. P.12) [5 pt] What impact does this have on the performance of the processor? Ans. A single-cycle design impacts the performance of the processor negatively. Since the clock cycle must have the same length for every instruction and the critical path in the processor determines the clock cycle. This path is most likely a LW instruction, which causes the overall performance to be poor due to a long clock cycle. ---------------------------------------Questions END here--------------------------------

Assignment #2 – Spring 2018, Exercises of Computer Science

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